DS64BR111_13 Datasheet, PDF (25/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS64BR111
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Address
Register
Name
0x00
Device ID
0x01
Control 1
0x02
Control 2
0x04
Control 3
0x05
0x06
CRC 1
CRC 2
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
Table 9. SMBus Register Map
Bits
Field
7
Reserved
6:3 I2C Address [3:0]
2
EEPROM reading
done
1
Reserved
0
Reserved
7:6 Idle Control
5:3 Reserved
2
LOS Select
1:0 Reserved
7
Reserved
6
Reserved
5
LOS override
4
LOS override value
3
PWDN Inputs
2
PWDN Oscillator
1
Reserved
0
Reserved
7:6 eSATA Mode
Enable
5
TX_DIS Override
Enable
4
TX_DIS Value
Channel A
3
TX_DIS Value
Channel B
2
Reserved
1:0 EQ CONTROL
7:0 CRC[7:0]
7
Disable EEPROM
CFG
6:5 Reserved
4
Reserved
3
CRC Slave Mode
Disable
2:1 Reserved
0
CRC Enable
Type Default
R/W 0x00
R
R
RWS
C
RWS
C
R/W
0x00
R/W
R/W
R/W
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x10
EEPROM
Reg Bit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Description
set bit to 0
[6:3] SMBus strap observation
1: EEPROM Loading
0: EEPROM Done Loading
set bit to 0
set bit to 0
Control
[7]: Continuous talk ENABLE (Channel A)
[6]: Continuous talk ENABLE (Channel B)
[2]: LOS SEL Channel B
Set bits to 0
LOS Monitor Selection
1: Use LOS from CH B
0: Use LOS from CH A
Set bits to 00'b
Set bit to 0
Set bit to 0
LOS pin override enable (1);
Use Normal Signal Detection (0)
1: Normal Operation
0: Output LOS
1: PWDN
0: Normal Operation
Set bit to 0
[7] Channel A (1)
[6] Channel B (1)
1: Override Use Reg 0x04[4:3]
0: Normal Operation - uses pin
1: TX Disabled
0: TX Enabled
Set bit to 0
[1]: Channel B - EQ Stage 4 ON/OFF
[0]: Channel A - EQ Stage 4 ON/OFF
Slave Mode CRC Bits
Disable Master Mode EEPROM Configuration
Set bits to 0
Set bit to 1
[1]: CRC Disable (No CRC Check)
[0]: CRC Check ENABLE
Note: With CRC check DISABLED register
updates take immediate effect on high speed
data path. With CRC check ENABLED register
updates will NOT take effect until correct CRC
value is loaded
Set bits to 0
Slave CRC Trigger
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