DS64BR111_13 Datasheet, PDF (8/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS64BR111
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Conditions
Min
T_{ENVELOPE_DISTO}
RT
Active OOB timing
distortion, input active
time vs. output active
time
OUTPUT JITTER SPECIFICATIONS⁽⁵⁾
R_J
Random Jitter
No Media
Source Amplitude = 700 mV,
PRBS15 pattern,
6.4 Gbps
VOD = Default, EQ =
minimum, DE = 0 dB
D_J1
Equalization
Deterministic Jitter
D_JE1
Residual Deterministic
Jitter
10.3125 Gbps
8 meter 30AWG Cable on
Input
Source = 700 mV, PRBS15
pattern
EQ = 0F'h; See Figure 15
D_JE2
Residual Deterministic
Jitter
6.4 Gbps
30" FR4 on Inputs
Source = 800 mV, PRBS15
pattern
EQ = 16'h; See Figure 13
De-emphasis
D_JD1
Residual Deterministic
Jitter
6.4 Gbps
10” 4 mil stripline FR4 on
Outputs
Source = 700 mV, PRBS15
pattern
EQ = 00 (Min), DE = 010'b
See Figure 17
Typ
Max
3.3
0.35
0.065
0.15
0.10
0.085
(5) Typical jitter reported is determined by jitter decomposition software on a DSA8200 Oscilloscope.
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Units
ns
ps (RMS)
UI
UI
UI
UI
ELECTRICAL CHARACTERISTICS — SERIAL MANAGEMENT BUS INTERFACE
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
SERIAL BUS INTERFACE DC SPECIFICATIONS:⁽¹⁾
Conditions
Min
Typ
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Capacitance for SDA and SCL
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
See ⁽²⁾
See⁽²⁾ and ^{(3) (4)}
Pullup V_DD = 3.3V^{(2) (3)(5)}
Pullup V_DD = 2.5V^{(2) (3)(5)}
2.375
-200
2000
1000
SERIAL BUS INTERFACE TIMING SPECIFICATIONS
FSMB
Bus Operating Frequency
ENSMB = VDD (Slave Mode)
ENSMB = FLOAT (Master Mode)
(2)
280
400
TBUF
Bus Free Time Between Stop and
Start Condition
1.3
Max
0.8
3.6
3.6
+200
10
400
520
Units
V
V
mA
V
µA
pF
Ω
Ω
kHz
kHz
µs
(1) EEPROM interface requires 400 KHz capable EEPROM device.
(2) Recommended value.
(3) Recommended maximum capacitance load per bus segment is 400pF.
(4) Specified by Design and/or characterization. Parameter not tested in production.
(5) Maximum termination voltage should be identical to the device supply voltage.
8
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