DS64BR111_13 Datasheet, PDF (15/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS64BR111
www.ti.com
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Please see SMBus Register Map Table for more information for more information.
Slave Address
Register Address
Slave Address
Data
S
Device
ID
+
A3
AAA
210
a
0c
k
7 65432 1 0
a
cS
k
Device
ID
+
A3
A
2
A
1
A
0
1
a
a
c 76543210 c P
k
k
Figure 5. Typical SMBus Write Operation
EEPROM Modes in DS64BR111 Device
The DS64BR111 device supports reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS64BR111 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these
specific guidelines.
• Set the DS64BR111 into SMBus Master Mode
– Float ENSMB (PIN 3)
• The external EEPROM device address byte must be 0xA0'h
• Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
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