DS64BR111_13 Datasheet, PDF (4/39 Pages) Texas Instruments – DS64BR111 Ultra Low Power 6.4 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

DS64BR111
SNLS343C – SEPTEMBER 2011 – REVISED APRIL 2013
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Pin Name
AD0-AD3
Pin
Number
10, 9, 2, 1
READEN#
17
DONE#
18
ENSMB = 0 (PIN MODE)
EQA0, EQA1
EQB0, EQB1
10, 9
1, 2
DEMA, DEMB
4, 5
TX_DIS
6
VOD_SEL
17
VDD_SEL
16
MODE
18
Status Output
LOS
13
LOS Threshold Input
SD_TH
14
Power
PIN DESCRIPTIONS (continued)
I/O, Type⁽¹⁾
Pin Description
I, LVCMOS Float
(4-Levels)
I, LVCMOS
IO, LVCMOS,
Float
(4-Levels)
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set
SMBus slave address inputs. There are 16 addresses supported by these
pins.
Pins must be tied LOW or HIGH when used to define the device SMBus
address.
Note: Setting VOD_SEL = High in SMBus Mode will force the Address =
B0'h
When using an External EEPROM, a transition from high to low starts the load
from the external EEPROM
EEPROM Download Status
HIGH indicates Error / Still Loading
LOW indicates download complete. No Error.
I, LVCMOS, Float
(4-Levels)
EQA/B ,0/1 control the level of equalization of each channel. The EQA/B pins
are active only when ENSMB is de-asserted (LOW).
When ENSMB goes high the SMBus registers provide independent control of
each lane, and the EQB0/B1 pins are converted to SMBUS AD2/AD3 inputs.
IO, LVCMOS,
Float
(4-Levels)
DEMA/B controls the level of de-emphasis. The DEMA/B pins are only active
when ENSMB is de-asserted (LOW). Each of the 4 A/B channels have the
same level unless controlled by the SMBus control registers. When ENSMB
goes high the SMBus registers provide independent control of each lane and
the DEM pins are converted to SMBUS SCL and SDA pins.
I, LVCMOS
DS64BR111
High = OUTA Enabled / OUTB Disabled
Low = OUTA/B Enabled
I, LVCMOS, Float
(4-Levels)
EQ Mode and VOD select.
High = (VOD = 1.1V/1.3V)
Float = (VOD = 1.0 V)
20K = (VOD = 1.2 V)
Low = (VOD = 700m V)
Note: DS64BR111 OUTA is limited to 700mV in pin mode, see Table 4 for
additional information.
Note: Setting VOD_SEL = High in SMBus Mode will force the SMBus
Address = B0'h
I, Internal Pull-up Enables the 3.3V to 2.5V internal regulator
Low = 3.3 V Operation
Float = 2.5 V Operation
I, LVCMOS
Controls Device Mode of Operation
High = Continuous Talk
Float = Slow OOB
20KΩ = eSATA Mode, Fast OOB, Auto Low Power on 100 uS of inactivity. SD
stays active.
Low = SAS Mode, Fast OOB
O, Open Drain
Indicates Loss of Signal (Default is LOS on INA). Can be modified via SMBus
registers.
I, LVCMOS, Float
(4-Levels)
The SD_TH pin controls LOS threshold setting;
Assert (mV), Deassert (mV)
20K = 160 mV, 100 mV
Float = 180 mV, 110 mV (Default)
High = 190 mV, 130 mV
Low = 210 mV, 150 mV
Note: Using values less than the default level can extend the time
required to detect LOS and are not recommended.
4
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