DS100MB201_16 Datasheet, PDF (9/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization

DS100MB201
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Functional Description
SNLS333A – APRIL 2011 – REVISED APRIL 2013
The DS100MB201 is a 2–lane signal conditioning 2:1 multiplexer and 1:2 switch or fan-out buffer optimized for
PCB FR4 trace up to 10.3125 Gbps data rate. The DS100MB201 has direct register access through the SMBus.
The ENSMB pin must be tied high to enable proper operation of the DS100MB201.
Pin Control Mode
The RATE pin must be forced HIGH to enable 10.3125 Gbps operation. The receiver electrical idle detect
threshold is also programmable via an optional external resistor on the SD_TH pin.
SMBUS Register Programming
In SMBus mode the VOD amplitude level and equalization are all programmable on a individual lane basis. On
power-up and when ENSMB is driven low all registers are reset to their default state.
TXIDLEDO/SO
0
Float
1
Table 1. Idle Control (3–Level Input)
Function
This state is for lossy media, dedicated Idle threshold detect circuit disabled,
output follows input based on EQ settings. Idle state not guaranteed.
Float enables automatic idle detection. Idle on the input is passed to the
output. Internal 50KΩ resistors hold TXIDLEDO/SO pin at a mid level - don't
connect this pin if the automatic idle detect function is desired. This is the
default state. Output in Idle if differential input signal less than value set by
SD_TH pin.
Manual override, output in electrical Idle. Differential inputs are ignored.
Table 2. Receiver Electrical Idle Detect Threshold Adjust
SD_TH resistor value (Ω)
Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130 mV (default condition)
0
225 mV
80k
20 mV
SD_TH resistor value can be set from 0 through 80k ohms to achieve desired idle detect threshold, see Figure 6
250
V_DD = 2.5V
T_A = 25°C
200
150
100
50
0
0 10k 20k 30k 40k 50k 60k 70k 80k
SD_TH RESISTOR VALUE (:)
Figure 6. Typical Idle Threshold vs. SD_TH resistor value
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