DS100MB201_16 Datasheet, PDF (11/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization

DS100MB201
www.ti.com
SNLS333A – APRIL 2011 – REVISED APRIL 2013
TRANSFER OF DATA VIA THE SMBUS
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.
SMBUS TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
When SMBus is enabled, all outputs of the DS100MB201 must write VOD2 register to 0x01 (hex). See Table 4
for more information. Each channel must be set to the value of 0x01 (hex) through each register (0x18, 0x26,
0x2E, 0x35, 0x3C, 0x43) to ensure a proper output waveform. The driver Vout voltage is set on a per lane basis
using 6 different registers. Each register (0x17, 0x25, 0x2D, 0x34, 0x3B, 0x43) controls the VOD to 600 mV and
800 mV.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1” indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
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