DS100MB201_16 Datasheet, PDF (7/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization

DS100MB201
www.ti.com
SNLS333A – APRIL 2011 – REVISED APRIL 2013
Electrical Characteristics⁽¹⁾ (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min
Typ
Max
EQUALIZATION
DJ1
Residual Deterministic Jitter at 8.5 Tx Launch Amplitude = 0.8 to
Gbps
1.2 Vp–p, 10” 4–mil FR4 trace,
VOD = 0.8 Vp-p, K28.5, SD_TH = float
0.1
0.25
DJ2
Residual Deterministic Jitter at
Tx Launch Amplitude = 0.8 to
10.3125 Gbps
1.2 Vp–p, 10” 4–mil FR4 trace,
VOD = 0.8 Vp-p, K28.5, SD_TH = float
0.1
0.3
RJ
Random Jitter
Tx Launch Amplitude = 1.2 Vp–p,
Repeating 1100b (D24.3) pattern
0.5
Units
UI_P-P
UI_P-P
ps_rms
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Parameter
Test Conditions
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL
V_IH
I_PULLUP
Data, Clock Input Low Voltage
Data, Clock Input High Voltage
Current Through Pull-Up Resistor
or Current Source
High Power Specification
V_DD
I_LEAK-Bus
I_LEAK-Pin
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SCL
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
See ⁽¹⁾
See ^{(1) (2)}
V_DD3.3, See^{(1) (2) (3)}
V_DD2.5, See^{(1) (2) (3)}
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 5
FSMB
Bus Operating Frequency
See ⁽⁴⁾
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO Stop Condition Setup Time
THD:DAT Data Hold Time
TSU:DAT
T_TIMEOUT
T_LOW
T_HIGH
T_LOW:SEXT
t_F
t_R
t_POR
Data Setup Time
Detect Clock Low Timeout
See ⁽⁴⁾
Clock Low Period
Clock High Period
Cumulative Clock Low Extend Time
(Slave Device)
Clock/Data Fall Time
Clock/Data Rise Time
Time in which a device must be
operational after power-on reset
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
See ⁽⁴⁾
Min
2.1
4
2.375
-200
10
4.7
4.0
4.7
4.0
300
250
25
4.7
4.0
Typ
-15
2000
1000
Max
0.8
3.6
3.6
+200
10
100
35
50
2
300
1000
500
Units
V
V
mA
V
µA
µA
pF
Ω
Ω
kHz
µs
µs
µs
µs
ns
ns
ms
µs
µs
ms
ns
ns
ms
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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