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DS100MB201_16 Datasheet, PDF (2/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization
DS100MB201
SNLS333A – APRIL 2011 – REVISED APRIL 2013
Pin Diagram
SMBUS AND CONTROL
NC 1
NC 2
DOUT0+ 3
DOUT0- 4
NC 5
NC 6
DOUT1+ 7
DOUT1- 8
VDD 9
DIN0+ 10
DIN0- 11
NC 12
NC 13
VDD 14
DIN1+ 15
DIN1- 16
NC 17
NC 18
TOP VIEW
DAP = GND
45 SIA0+
44 SIA0-
43 SIB0+
42 SIB0-
41 VDD
40 SIA1+
39 SIA1-
38 SIB1+
37 SIB1-
36 VDD
35 SOA0+
34 SOA0-
33 SOB0+
32 SOB0-
31 SOA1+
30 SOA1-
29 SOB1+
28 SOB1-
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Figure 1. DS100MB201 Pin Diagram 54L WQFN Package
See Package Number NJY0054A
Pin Name
Pin Number
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
SOA0+, SOA0-,
SOA1+, SOA1-
SIB0+, SIB0-,
SIB1+, SIB1-
35, 34,
31, 30
43, 42,
38, 37
SOB0+, SOB0-,
SOB1+, SOB1-
DIN0+, DIN0-,
DIN1+, DIN1-
33, 32,
29, 28
10, 11,
15, 16
PIN DESCRIPTIONS(1)
I/O, Type (2) (3) (4)
Pin Description
I, CML
O
I, CML
O
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-
chip 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD
when enabled.
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-
chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-
chip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
(1) 1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
(2) FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
(3) Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
(4) Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
2
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