DS100MB201_16 Datasheet, PDF (3/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization

DS100MB201
www.ti.com
SNLS333A – APRIL 2011 – REVISED APRIL 2013
PIN DESCRIPTIONS⁽¹⁾ (continued)
Pin Name
Pin Number
I/O, Type ^{(2) (3) (4)}
Pin Description
DOUT0+, DOUT0-, 3, 4,
O
DOUT1+, DOUT1- 7, 8
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
Control Pins — (LVCMOS)
ENSMB
48
I, LVCMOS w/
internal pull-down
System Management Bus (SMBus) enable pin.
LOW = Reserved
HIGH = Register Access: Provides access to internal digital registers to control
such functions as equalization, VOD, channel powerdown, and idle detection
threshold.
Please refer to System Management Bus (SMBus) and Configuration
Registers for detailed information.
SDA
SCL
49
I, LVCMOS
The SMBus bi-directional SDA pin. Data input or open drain output. External
pull-up resistor is required. Refer to R_term in the SMBus specification.
50
I, LVCMOS
SMBUS clock input pin. External pull-up resistor maybe needed. Refer to R_term
in the SMBus specification.
AD[3:0]
46, 47, 53, 54 I, LVCMOS w/
SMBus Slave Address Inputs. These pins set the SMBus address.
internal pull-down
Control Pins — (LVCMOS)
RATE
21
I, Float, LVCMOS LOW = Reserved
HIGH = 10.3125 Gbps operation
TXIDLEDO
24
I, Float, LVCMOS
TXIDLEDO, 3–level input controls the driver output.
LOW = disable the signal detect/squelch function for DOUT.
FLOAT = enable the signal auto detect/squelch function for DOUT and the
signal detect voltage threshold level can be adjusted using the SD_TH pin.
HIGH = force the DOUT to be muted (electrical idle). See Table 1
TXIDLESO
25
I, Float, LVCMOS
TXIDLESO, 3–level input controls the driver output.
LOW = disable the signal detect/squelch function for SOUT.
FLOAT = enable the signal auto detect/squelch function for SOUT and the
signal detect voltage threshold level can be adjusted using the SD_TH pin.
HIGH = force the SOUT to be muted (electrical idle). See Table 1
FANOUT
26
I, LVCMOS w/
internal pull-down
LOW = disable one of the outputs depending on the SEL0, SEL1 pin.
HIGH = enable both A/B outputs for broadcast mode.
FANOUT = 0 See Table 3
SEL0, SEL1
19, 20
I, LVCMOS w/
internal pull-down
SEL0 is for lane 0, SEL1 is for lane 1
SEL0, SEL1 = 0 selects B input and B output.
SEL0, SEL1 = 1 selects A input and A output. See Table 3
Reserved
52
I, LVCMOS
Tie to GND
Analog
SD_TH
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for default
130 mVp-p (differential).
See Table 2
Power
VDD
9, 14, 36, 41, 51 Power
2.5V Power supply pins.
GND
DAP
Power
DAP is the large metal contact at the bottom side, located at the center of the
54 pin LLP package. It should be connected to the GND plane with at least 4
via to lower the ground impedance and improve the thermal performance of
the package.
Reserved
1, 2, 5, 6, 12,
13, 17, 18, 22,
23
No Connect — Leave pin open
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2011–2013, Texas Instruments Incorporated
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