DS100MB201_16 Datasheet, PDF (8/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization

DS100MB201
SNLS333A – APRIL 2011 – REVISED APRIL 2013
Timing Diagrams
Figure 2. Output Transition Times
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Figure 3. Propagation Delay Timing Diagram
Figure 4. Idle Timing Diagram
t_LOW
t_R
t_BUF
t_HD:STA
t_HD:DAT
t_HIGH
t_F
t_SU:DAT
t_SU:STA
t_SU:STO
SP
ST
ST
SP
Figure 5. SMBus Timing Parameters
SCL
SDA
8
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