DS100MB201_16 Datasheet, PDF (12/26 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization

DS100MB201
SNLS333A – APRIL 2011 – REVISED APRIL 2013
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RECOMMENDED SMBUS REGISTER SETTINGS
Upon power-up, the default register settings are not configured to an appropriate level. Below is the
recommended settings to configure the EQ and VOD to a medium level that supports interconnect length of 10
inches FR4 trace. Please refer to Table 4, Table 5 for additional information and recommended settings.
1. Reset the SMBus registers to default values:
– Write 01'h to 0x00.
2. Set output voltage for all lanes:
– Write 01'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization ~6 dB at 5GHz for all lanes:
– Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 0.8 Vp-p for all lanes:
– Write 07'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
Table 4. Output Driver Register Settings (must write when in SMBus mode)
Output Value
1V dB
VOD Control 1
Register Setting
(800 mV)
0x07
VOD Control 2
Register Setting (must set)
0x01
10.3125 Gbps Operation
10” trace
Address
Register Name
0x00
Reset
0x01
PWDN lanes
0x02
PWDN Control
0x03
SEL / FANOUT
Control
0x08
Pin Control Override
Table 5. SMBus Register Map
Bit(s)
Field
7:1 Reserved
0
Reset
7:0 PWDN CHx
7:1 Reserved
0
PWDN Control
7:3 Reserved
2
SEL1
1
SEL0
0
FANOUT
7:5 Reserved
4
Override IDLE
3
Reserved
2
Reserved
1
Override SEL
0
Override
FANOUT
Type
R/W
R/W
R/W
R/W
R/W
Default
0x00
0x00
0x00
0x00
0x00
Description
Set bits to 0.
SMBus Reset
1: Reset registers to default value
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
Set bits to 0.
0: Normal operation
1: Enable PWDN control in Register 0x01
Set bits to 0.
0: Selects B input and output
1: Selects A input and output
0: Selects B input and output
1: Selects A input and output
0: Enable only A or B output depends on SEL1 and
SEL0
1: Enable both A and B output
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
Set bit to 0.
0: Allow SEL pin control
1: Block SEL pin control
0: Allow FANOUT pin control
1: Block FANOUT pin control
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