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COP888CL Datasheet, PDF (9/42 Pages) Texas Instruments – COP888CL 8-Bit Microcontroller
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DC Electrical Characteristics (Continued)
COP88XCL: −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (Min)
Input Capacitance
Load Capacitance on D2
Min
Typ
2
Max
7
1000
Units
V
pF
pF
Note 9: Rate of voltage change must be less then 0.5 V/ms.
Note 10: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 11: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured
as outputs and set high. The D port set to zero. The clock monitor is disabled.
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Instruction Cycle Time (tc)
Crystal or Resonator
R/C Oscillator
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 13)
tPD1, tPD0
SO, SK
All Others
MICROWIRE Setup Time (tUWS)
MICROWIRE Hold Time (tUWH)
MICROWIRE Output Propagation Delay (tUPD)
Input Pulse Width
Interrupt Input High Time
Interrupt Input Low Time
Timer Input High Time
Timer Input Low Time
Reset Pulse Width
Conditions
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
RL = 2.2k, CL = 100 pF
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
Min
Typ
1
2.5
3
7.5
200
500
60
150
Max
DC
DC
DC
DC
Units
µs
µs
µs
µs
ns
ns
ns
ns
0.7
µs
1.75
µs
1
µs
2.5
µs
20
ns
56
ns
220
ns
1
tc
1
tc
1
tc
1
tc
1
µs
Note 12: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 13: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
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