COP888CL Datasheet, PDF(23/42 Page) Texas Instruments

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

COP888CL Datasheet, PDF (23/42 Pages) Texas Instruments – COP888CL 8-Bit Microcontroller

◁

Interrupts (Continued)

Arbitration

Ranking

Source

Description

(1) Highest

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10) Lowest

Software

Reserved

External

Timer T0

Timer T1

MICROWIRE/PLUS

Reserved

Timer T2

Reserved

Port L/Wakeup

Default

INTR Instruction

for Future Use

Pin G0 Edge

Underflow

T1A/Underflow

T1B

BUSY Goes Low

for Future Use

for UART

T2A/Underflow

T2B

for Future Use

Port L Edge

VIS Instr. Execution

without Any Interrupts

Vector

Address

Hi-Low Byte

0yFEâ0yFF

0yFCâ0yFD

0yFAâ0yFB

0yF8â0yF9

0yF6â0yF7

0yF4â0yF5

0yF2â0yF3

0yF0â0yF1

0yEEâ0yEF

0yECâ0yED

0yEAâ0yEB

0yE8â0yE9

0yE6â0yE7

0yE4â0yE5

0yE2â0yE3

0yE0â0yE1

y is VIS page, y â 0.

At this time, since GIE = 0, other maskable interrupts are

disabled. The user is now free to do whatever context

switching is required by saving the context of the machine in

the stack with PUSH instructions. The user would then pro-

gram a VIS (Vector Interrupt Select) instruction in order to

branch to the interrupt service routine of the highest priority

interrupt enabled and pending at the time of the VIS. Note

that this is not necessarily the interrupt that caused the

branch to address location 00FF Hex prior to the context

switching.

Thus, if an interrupt with a higher rank than the one which

caused the interruption becomes active before the decision

of which interrupt to service is made by the VIS, then the

interrupt with the higher rank will override any lower ones

and will be acknowledged. The lower priority interrupt(s) are

still pending, however, and will cause another interrupt im-

mediately following the completion of the interrupt service

routine associated with the higher priority interrupt just ser-

viced. This lower priority interrupt will occur immediately

following the RETI (Return from Interrupt) instruction at the

end of the interrupt service routine just completed.

Inside the interrupt service routine, the associated pending

bit has to be cleared by software. The RETI (Return from

Interrupt) instruction at the end of the interrupt service rou-

tine will set the GIE (Global Interrupt Enable) bit, allowing the

processor to be interrupted again if another interrupt is active

and pending.

The VIS instruction looks at all the active interrupts at the

time it is executed and performs an indirect jump to the

beginning of the service routine of the one with the highest

rank.

The addresses of the different interrupt service routines,

called vectors, are chosen by the user and stored in ROM in

a table starting at 01E0 (assuming that VIS is located be-

tween 00FF and 01DF). The vectors are 15-bit wide and

therefore occupy 2 ROM locations.

VIS and the vector table must be located in the same

256-byte block (0y00 to 0yFF) except if VIS is located at the

last address of a block. In this case, the table must be in the

next block. The vector table cannot be inserted in the first

256-byte block.

The vector of the maskable interrupt with the lowest rank is

located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)

and so forth in increasing rank number. The vector of the

maskable interrupt with the highest rank is located at 0yFA

(Hi-Order byte) and 0yFB (Lo-Order byte).

The Software Trap has the highest rank and its vector is

located at 0yFE and 0yFF.

If, by accident, a VIS gets executed and no interrupt is

active, then the PC (Program Counter) will branch to a vector

located at 0yE0â0yE1.

WARNING

A Default VIS interrupt handle routine must be present. As a

minimum, this handler should confirm that the GIE bit is

cleared (this indicates that the interrupt sequence has been

taken), take care of any required housekeeping, restore

context and return. Some sort of Warm Restart procedure

should be implemented. These events can occur without any

error on the part of the system designer or programmer.

Note: There is always the possibility of an interrupt occurring during an

instruction which is attempting to reset the GIE bit or any other inter-

rupt enable bit. If this occurs when a single cycle instruction is being

used to reset the interrupt enable bit, the interrupt enable bit will be

reset but an interrupt may still occur. This is because interrupt process-

ing is started at the same time as the interrupt bit is being reset. To

avoid this scenario, the user should always use a two, three, or four

cycle instruction to reset interrupt enable bits.

Figure 12 shows the Interrupt block diagram.

www.national.com

▷