COP888CL Datasheet, PDF (25/42 Pages) Texas Instruments – COP888CL 8-Bit Microcontroller

WATCHDOG Operation (Continued)
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, in-
cluding the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCH-
DOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table 5 shows the se-
quence of events that can occur.
The user must service the WATCHDOG at least once before
the upper limit of the serivce window expires. The WATCH-
DOG may not be serviced more than once in every lower
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional 16 t_c–32
t_c cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the device
will stop forcing the WDOUT output low.
The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to V_CC through a resistor in order to
pull WDOUT high.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will enter high impedance state.
TABLE 5. WATCHDOG Service Actions
Key
Data
Match
Don’t Care
Mismatch
Don’t Care
Window
Data
Match
Mismatch
Don’t Care
Don’t Care
Clock
Monitor
Match
Don’t Care
Don’t Care
Mismatch
Action
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
Error: Generate WATCHDOG Output
TABLE 6. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
SK
0
0
2 x t_c
0
1
4 x t_c
1
x
8 x t_c
Where t_c is the instruction cycle clock
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will enter the high imped-
ance TRI-STATE mode following 16 t_c–32 t_c clock cycles.
The Clock Monitor generates a continual Clock Monitor error
if the oscillator fails to start, or fails to reach the minimum
specified frequency. The specification for the Clock Monitor
is as follows:
1/t_c > 10 kHz — No clock rejection.
1/t_c < 10 Hz — Guaranteed clock rejection.
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
Clock Monitor should be noted:
• Both WATCHDOG and Clock Monitor detector circuits
are inhibited during reset.
• Following reset, the WATCHDOG and Clock Monitor are
both enabled, with the WATCHDOG having the maximum
service window selected.
• The WATCHDOG service window and Clock Monitor
enable/disable option can only be changed once, during
the initial WATCHDOG service following reset.
• The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in
order to avoid a WATCHDOG error.
• Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG
errors.
• The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
• The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
• The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected as
a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).
• With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service win-
dow will resume following HALT mode from where it left
off before entering the HALT mode.
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