COP888CL Datasheet, PDF (22/42 Pages) Texas Instruments – COP888CL 8-Bit Microcontroller

Multi-Input Wakeup (Continued)
FIGURE 11. Multi-Input Wake Up Logic
DS009766-16
PORT L INTERRUPTS
Port L provides the user with an additional eight fully select-
able, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake up
circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable inter-
rupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the in-
struction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the
interrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immedi-
ately since crystal oscillators or ceramic resonators have a
finite start up time. The IDLE Timer (T0) generates a fixed
delay to ensure that the oscillator has indeed stabilized
before allowing the device to execute instructions. In this
case, upon detecting a valid Wakeup signal, only the oscil-
lator circuitry and the IDLE Timer T0 are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
t_c instruction cycle clock. The t_c clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE
timer is clocked only when the oscillator has a sufficiently
large amplitude to meet the Schmitt trigger specifications.
This Schmitt trigger is not part of the oscillator closed loop.
The startup timeout from the IDLE timer enables the clock
signals to be routed to the rest of the chip. If the RC clock
option is used, the fixed delay is under software control. A
control flag, CLKDLY, in the G7 configuration bit allows the
clock start up delay to be optionally inserted. Setting
CLKDLY flag high will cause clock start up delay to be
inserted and resetting it will exclude the clock start up delay.
The CLKDLY flag is cleared during reset, so the clock start
up delay is not present following reset with the RC clock
options.
Interrupts
The device supports a vectored interrupt scheme. It supports
a total of ten interrupt sources. The following table lists all the
possible interrupt sources, their arbitration ranking and the
memory locations reserved for the interrupt vector for each
source.
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt is
active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will be
interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described in
the Software Trap sub-section.
The interruption process is accomplished with the INTR
instruction (opcode 00), which is jammed inside the Instruc-
tion Register and replaces the opcode about to be executed.
The following steps are performed for every interrupt:
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address 00FF.
This procedure takes 7 t_c cycles to execute.
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