COP888CL Datasheet, PDF(14/42 Page) Texas Instruments

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

COP888CL Datasheet, PDF (14/42 Pages) Texas Instruments – COP888CL 8-Bit Microcontroller

◁

Pin Descriptions (Continued)

PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers

on the inputs.

Port L supports Multi-Input Wakeup (MIWU) on all eight pins.

L4 and L5 are used for the timer input functions T2A and

T2B.

Port L has the following alternate features:

L0 MIWU

L1 MIWU

L2 MIWU

L3 MIWU

L4 MIWU or T2A

L5 MIWU or T2B

L6 MIWU

L7 MIWU

Port G is an 8-bit port with 5 I/O pins (G0, G2âG5), an input

pin (G6), and two dedicated output pins (G1 and G7). Pins

G0 and G2âG6 all have Schmitt Triggers on their inputs. Pin

G1 serves as the dedicated WDOUT WATCHDOG output,

while pin G7 is either input or output depending on the

oscillator mask option selected. With the crystal oscillator

option selected, G7 serves as the dedicated output pin for

the CKO clock output. With the single-pin R/C oscillator

mask option selected, G7 serves as a general purpose input

pin, but is also used to bring the device out of HALT mode

with a low to high transition. There are two registers associ-

ated with the G Port, a data register and a configuration

be individually configured under software control.

Since G6 is an input only pin and G7 is the dedicated CKO

clock output pin or general purpose input (R/C clock configu-

ration), the associated bits in the data and configuration

registers for G6 and G7 are used for special purpose func-

tions as outlined below. Reading the G6 and G7 data bits will

return zeros.

Note that the chip will be placed in the HALT mode by writing

a â1â to bit 7 of the Port G Data Register. Similarly the chip

will be placed in the IDLE mode by writing a â1â to bit 6 of the

Port G Data Register.

Writing a â1â to bit 6 of the Port G Configuration Register

enables the MICROWIRE/PLUS to operate with the alter-

nate phase of the SK clock. The G7 configuration bit, if set

high, enables the clock start up delay after HALT when the

R/C clock configuration is used.

Config Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

G0 INTR (External Interrupt Input)

G2 T1B (Timer T1 Capture Input)

G3 T1A (Timer T1 I/O)

G4 SO (MICROWIRE Serial Data Output)

G5 SK (MICROWIRE Serial Clock)

G6 SI (MICROWIRE Serial Data Input)

Port G has the following dedicated functions:

G1 WDOUT WATCHDOG and/or Clock Monitor dedi-

cated output

G7 CKO Oscillator dedicated output or general purpose

input

Port C is an 8-bit I/O port. The 40-pin device does not have

a full complement of Port C pins. The unavailable pins are

not terminated. A read operation for these unterminated pins

will return unpredictable values.

Port I is an 8-bit Hi-Z input port. The 40-pin device does not

have a full complement of Port I pins. Pins 15 and 16 on this

package must be connected to GND.

The 28-pin device has four I pins (I0, I1, I4, I5). The user

should pay attention when reading port I to the fact that I4

and I5 are in bit positions 4 and 5 rather than 2 and 3.

The unavailable pins (I4âI7) are not terminated i.e., they are

floating. A read operation for these unterminated pins will

return unpredictable values. The user must ensure that the

software takes into account by either masking or restricting

the accesses to bit operations. The unterminated port I pins

will draw power only when addressed.

Port D is an 8-bit output port that is preset high when RESET

goes low. The user can tie two or more D port outputs

(except D2) together in order to get a higher drive.

Note: Care must be exercised with the D2 pin operation. At RESET, the

external loads on this pin must ensure that the output voltages stay

above 0.8 VCC to prevent the chip from entering special modes. Also

keep the external loading on D2 to less than 1000 pF.

Functional Description

The architecture of the device is modified Harvard architec-

ture. With the Harvard architecture, the control store pro-

gram memory (ROM) is separated from the data store

memory (RAM). Both ROM and RAM have their own sepa-

rate addressing space with separate address buses. The

architecture, though based on Harvard architecture, permits

transfer of data from ROM to RAM.

CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift

operation in one instruction (tc) cycle time.

There are five CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally

post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be

optionally post auto incremented or decremented.

SP is the 8-bit stack pointer, which points to the subroutine/

interrupt stack (in RAM). The SP is initialized to RAM ad-

dress 06F with reset.

All the CPU registers are memory mapped with the excep-

tion of the Accumulator (A) and the Program Counter (PC).

PROGRAM MEMORY

Program memory consists of 4096 bytes of ROM. These

bytes may hold program instructions or constant data (data

tables for the LAID instruction, jump vectors for the JID

instruction, and interrupt vectors for the VIS instruction). The

program memory is addressed by the 15-bit program

counter (PC). All interrupts vector to program memory loca-

tion 0FF Hex.

www.national.com

▷