COP888CL Datasheet, PDF (24/42 Pages) Texas Instruments – COP888CL 8-Bit Microcontroller

Interrupts (Continued)
FIGURE 12. Interrupt Block Diagram
DS009766-18
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the PC
is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but not
necessarily containing all of the same initialization proce-
dures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This pending bit is also
cleared on reset.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
“runaway” programs. The Clock Monitor is used to detect the
absence of a clock or a very slow clock below a specified
rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is com-
posed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 3 shows the WDSVR register.
The lower limit of the service window is fixed at 2048 instruc-
tion cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 4 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flex-
ibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
TABLE 3. WATCHDOG Service Register (WDSVR)
Window
Select
X
X
7
6
Key Data
Clock
Monitor
01100
Y
54321
0
TABLE 4. WATCHDOG Service Window Select
WDSVR
Bit 7
0
0
1
1
WDSVR
Bit 6
0
1
0
1
Service Window
(Lower-Upper Limits)
2k-8k t_c Cycles
2k-16k t_c Cycles
2k-32k t_c Cycles
2k-64k t_c Cycles
Clock Monitor
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/t_c) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
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