ADS1218_14 Datasheet, PDF (9/45 Pages) Texas Instruments – 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory

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TIMING SPECIFICATIONS
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
CS
t₃
t₁
SCLK
(POL = 0)
SCLK
(POL = 1)
t₄
t₅
D_IN
MSB
t₂
t₆
LSB
D_OUT
t₇
(Command or Command and Data)
NOTE: (1) Bit Order = 0.
t₂
t₈
MSB⁽¹⁾
t₁₀
t₁₁
t₉
LSB⁽¹⁾
TIMING SPECIFICATION TABLE
SPEC
t1
DESCRIPTION
SCLK Period
t2
SCLK Pulse Width, High and Low
t3
CS Low to first SCLK Edge; Setup Time
t4
DIN Valid to SCLK Edge; Setup Time
t5
Valid DIN to SCLK Edge; Hold Time
t6
Delay between last SCLK edge for DIN and first SCLK edge for DOUT:
RDATA, RDATAC, RREG, WREG, RRAM
CSREG, CSRAMX, CSRAM
CSARAM, CSARAMX
t7 ⁽¹⁾
SCLK Edge to Valid New DOUT
t8 ⁽¹⁾
SCLK Edge to DOUT, Hold Time
t9
Last SCLK Edge to DOUT Tri-State
NOTE: DOUT goes tri-state immediately when CS goes High.
t10
CS Low time after final SCLK edge
t11
Final SCLK edge of one op code until first edge SCLK of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM,
CSREG, SLEEP, RDATA, RDATAC, STOPC
DSYNC
CSFL
CREG, CRAM
RF2R
CREGA
WR2F
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (Command, SCLK, or Pin)
(1) Load = 20pF | | 10kΩ to DGND.
MIN
4
200
0
50
50
50
200
1100
0
6
0
4
16
33,000
220
1090
1600
76,850 (SPEED = 0)
101,050 (SPEED = 1)
7
14
2640
MAX
3
50
10
4
UNIT
tOSC Periods
DRDY Periods
ns
ns
ns
ns
tOSC Periods
tOSC Periods
tOSC Periods
ns
ns
tOSC Periods
ns
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
9