ADS1218_14 Datasheet, PDF (20/45 Pages) Texas Instruments – 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory

ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input, clocks data transfer
on the D_IN input and D_OUT output. When transferring
data to or from the ADS1218, multiple bits of data
may be transferred back-to-back with no delay in
SCLKs or toggling of CS. Make sure to avoid glitches
on SCLK because they can cause extra shifting of the
data.
Polarity (POL)
The serial clock polarity is specified by the POL input.
When SCLK is active high, set POL high. When
SCLK is active low, set POL low.
DATA READY
The DRDY output is used as a status signal to
indicate when data is ready to be read from the
ADS1218. DRDY goes low when new data is
available. It is reset high when a read operation from
the data register is complete. It also goes high prior
to the updating of the output register to indicate when
not to read from the device to ensure that a data read
is not attempted while the register is being updated.
DSYNC OPERATION
DSYNC is used to provide for synchronization of the
A/D conversion with an external event.
Synchronization can be achieved either through the
DSYNC pin or the DSYNC command. When the
DSYNC pin is used, the filter counter is reset on the
falling edge of DSYNC. The modulator is held in reset
until DSYNC is taken high. Synchronization occurs on
the next rising edge of the system clock after DSYNC
is taken high.
MEMORY
Three types of memory are used on the ADS1218:
registers, RAM, and Flash. 16 registers directly
control the various functions (PGA, DAC value,
Decimation Ratio, etc.) and can be directly read or
written to. Collectively, the registers contain all the
information needed to configure the part, such as
data format, mux settings, calibration settings,
decimation ratio, etc. Additional registers, such as
conversion data, are accessed through dedicated
instructions.
The on-chip Flash can be used to store non-volatile
data. The Flash data is separate from the
configuration registers and therefore can be used for
any purpose, in addition to device configuration. The
Flash page data is read and written in 128 byte
blocks through the RAM banks; for example, all RAM
banks map to a single page of Flash, as shown in
Figure 29.
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REGISTER BANK
The operation of the device is set up through
individual registers. The set of the 16 registers
required to configure the device is referred to as a
Register Bank, as shown in Figure 29.
Configuration
Register Bank
16 bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RAM
128 Bytes
Bank 0
16 bytes
FLASH
4k Bytes
Bank 2
16 bytes
Page 0
128 bytes
Bank 7
16 bytes
Page 31
128 bytes
Figure 29. Memory Organization
RAM
Reads and Writes to Registers and RAM occur on a
byte basis. However, copies between registers and
RAM occurs on a bank basis. The RAM is
independent of the Registers; for example, the RAM
can be used as general-purpose RAM.
The ADS1218 supports any combination of eight
analog inputs. With this flexibility, the device could
easily support eight unique configurations—one per
input channel. In order to facilitate this type of usage,
eight separate register banks are available.
Therefore, each configuration could be written once
and recalled as needed without having to serially
retransmit all the configuration data. Checksum
commands are also included, which can be used to
verify the integrity of RAM.