ADS1218_14 Datasheet, PDF (17/45 Pages) Texas Instruments – 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory

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PGA
The Programmable Gain Amplifier (PGA) can be set
to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the
PGA can improve the effective resolution of the A/D
converter. For instance, with a PGA of 1 on a 5V
full-scale range, the A/D converter can resolve to
1µV. With a PGA of 128, on a 40mV full-scale range,
the A/D converter can resolve to 75nV.
PGA OFFSET DAC
The input to the PGA can be shifted by half the
full-scale input range of the PGA by using the ODAC
register. The ODAC (Offset DAC) register is an 8-bit
value; the MSB is the sign and the seven LSBs
provide the magnitude of the offset. Using the ODAC
register does not reduce the performance of the A/D
converter. See Application Report The Offset DAC
(SBAA077) for more information.
MODULATOR
The modulator is a single-loop second-order system.
The modulator runs at a clock speed (f_MOD) that is
derived from the external clock (f_OSC). The frequency
division is determined by the SPEED bit in the
SETUP register.
SPEED BIT
0
1
f_MOD
f_OSC/128
f_OSC/256
VOLTAGE REFERENCE INPUT
The ADS1218 uses a differential voltage reference
input. The input signal is measured against the
differential voltage V_REF ≡ (V_REF+) – (V_REF–). For
AV_DD = 5V, V_REF is typically 2.5V. For AV_DD = 3V,
V_REF is typically 1.25V. Due to the sampling nature of
the modulator, the reference input current increases
with higher modulator clock frequency (f_MOD) and
higher PGA settings.
ON-CHIP VOLTAGE REFERENCE
A selectable voltage reference (1.25V or 2.5V) is
available for supplying the voltage reference input. To
use, connect V_REF– to AGND and V_REF+ to V_REFOUT.
The enabling and voltage selection are controlled
through bits REF EN and REF HI in the setup
register. The 2.5V reference requires AV_DD = 5V.
When using the on-chip voltage reference, the
V_REFOUT pin should be bypassed with a 0.1µF
capacitor to AGND.
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
V_RCAP PIN
This pin provides a bypass cap for noise filtering on
internal V_REF circuitry only. As this is a sensitive pin,
place the capacitor as close as possible and avoid
any resistive loading. The recommended capacitor is
a 1000pF ceramic cap. If an external V_REF is used,
this pin can be left unconnected.
CLOCK GENERATOR
The clock source for the ADS1218 can be provided
from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be
provided to ensure startup and a stable clock
frequency; see Figure 26 and Table 1.
Crystal
X_IN
C₁
X_OUT
C₂
Figure 26. Crystal Connection
Table 1. Typical Clock Sources
CLOCK
SOURCE
Crystal
Crystal
Crystal
Crystal
FREQUENCY
2.4576
4.9152
4.9152
4.9152
C₁
0-20pF
0-20pF
0-20pF
0-20pF
C₂
PART NUMBER
0-20pF
0-20pF
0-20pF
0-20pF
ECS, ECSD 2.45 - 32
ECS, ECSL 4.91
ECS, ECSD 4.91
CTS, MP 042 4M9182
CALIBRATION
The offset and gain errors in the ADS1218, or the
complete system, can be reduced with calibration.
Internal calibration of the ADS1218 is called self
calibration. This is handled with three commands.
One command does both offset and gain calibration.
There is also a gain calibration command and an
offset calibration command. Each calibration process
takes seven t_DATA periods to complete. It takes 14
t_DATA periods to complete both an offset and gain
calibration. Self-gain calibration is optimized for PGA
gains less than 8. When using higher gains, system
gain calibration is recommended.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command
requires a zero differential input signal. It then
computes an offset that will nullify offset in the
system. The system gain command requires a
positive full-scale differential input signal. It then
computes a value to nullify gain errors in the system.
Each of these calibrations will take seven t_DATA
periods to complete.
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