ADS1218_14 Datasheet, PDF(22/45 Page) Texas Instruments – 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory

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ADS1218_14 Datasheet, PDF (22/45 Pages) Texas Instruments – 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory

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ADS1218

SBAS187C â SEPTEMBER 2001 â REVISED SEPTEMBER 2005

www.ti.com

ADDRESS

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

SETUP

MUX

ACR

IDAC1

IDAC2

ODAC

DIO

DIR

DEC0

M/DEC1

OCR0

OCR1

OCR2

FSR0

FSR1

FSR2

BIT 7

PSEL3

BOCS

IDAC1_7

IDAC2_7

SIGN

DIO_7

DIR_7

DEC07

DRDY

OCR07

OCR15

OCR23

FSR07

FSR15

FSR23

BIT 6

PSEL2

IDAC2R1

IDAC1_6

IDAC2_6

OSET_6

DIO_6

DIR_6

DEC06

U/B

OCR06

OCR14

OCR22

FSR06

FSR14

FSR22

Table 2. Registers

BIT 5

PSEL1

IDAC2R0

IDAC1_5

IDAC2_5

OSET_5

DIO_5

DIR_5

DEC05

SMODE1

OCR05

OCR13

OCR21

FSR05

FSR13

FSR21

BIT 4

SPEED

PSEL0

IDAC1R1

IDAC1_4

IDAC2_4

OSET_4

DIO_4

DIR_4

DEC04

SMODE0

OCR04

OCR12

OCR20

FSR04

FSR12

FSR20

BIT 3

REF EN

NSEL3

IDAC1R0

IDAC1_3

IDAC2_3

OSET_3

DIO_3

DIR_3

DEC03

WREN

OCR03

OCR11

OCR19

FSR03

FSR11

FSR19

BIT 2

REF HI

NSEL2

PGA2

IDAC1_2

IDAC2_2

OSET_2

DIO_2

DIR_2

DEC02

DEC10

OCR02

OCR10

OCR18

FSR02

FSR10

FSR18

BIT 1

BUF EN

NSEL1

PGA1

IDAC1_1

IDAC2_1

OSET_1

DIO_1

DIR_1

DEC01

DEC9

OCR01

OCR09

OCR17

FSR01

FSR09

FSR17

BIT 0

BIT ORDER

NSEL0

PGA0

IDAC1_0

IDAC2_0

OSET_0

DIO_0

DIR_0

DEC00

DEC8

OCR00

OCR08

OCR16

FSR00

FSR08

FSR16

DETAILED REGISTER DEFINITIONS

SETUP (Address 00H) Setup Register

Reset value is set by Flash memory page 0. Factory programmed to iii01110.

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

SPEED

REF EN

REF HI

BUF EN

BIT ORDER

bits 7-5 Factory Programmed Bits

bit 4 SPEED: Modulator Clock Speed

0 : fMOD = fOSC/128

1 : fMOD = fOSC/256

NOTE: When writing to Flash memory using the WR2F command, SPEED must be set as follows:

2.30MHz < fOSC < 3.12MHz â SPEED = 0

3.13MHz < fOSC < 4.12MHz â SPEED = 1

bit 3 REF EN: Internal Voltage Reference Enable

0 = Internal Voltage Reference Disabled

1 = Internal Voltage Reference Enabled

bit 2 REF HI: Internal Reference Voltage Select

0 = Internal Reference Voltage = 1.25V

1 = Internal Reference Voltage = 2.5V

bit 1 BUF EN: Buffer Enable

0 = Buffer Disabled

1 = Buffer Enabled

bit 0 BIT ORDER: Set Order Bits are Transmitted

0 = Most Significant Bit Transmitted First

1 = Least Significant Bit Transmitted First Data is always shifted into the part most significant bit first.

Data is always shifted out of the part most significant byte first. This configuration bit only controls the

bit order within the byte of data that is shifted out.

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