LM3S2793 Datasheet, PDF (860/1194 Pages) Texas Instruments – Stellaris® LM3S2793 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010
This register indicates the transmit interrupt status and interrupt masking control.
I2S Transmit Interrupt Status and Mask (I2STXISM)
Base 0x4005.4000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
FFI
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FFM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
Name
reserved
FFI
Type
RO
RO
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Transmit FIFO Service Request Interrupt
Value Description
0 The FIFO level is equal to or above the FIFO limit.
1 The FIFO level is below the FIFO limit.
15:1
reserved
RO
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FFM
R/W
0
FIFO Interrupt Mask
Value Description
0 The FIFO interrupt is masked and not sent to the CPU.
1 The FIFO interrupt is enabled to be sent to the interrupt
controller.
860
January 20, 2012
Texas Instruments-Production Data