LM3S2793 Datasheet, PDF (551/1194 Pages) Texas Instruments – Stellaris® LM3S2793 Microcontroller

Stellaris^® LM3S2793 Microcontroller
Table 11-4. General-Purpose Timer Capabilities (continued)
Mode
Timer Use
Count Direction
PWM
Individual
Down
a. The prescaler is only available when the timers are used individually
Counter Size
16-bit
Prescaler Size^a
-
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 563),
the GPTM Timer A Mode (GPTMTAMR) register (see page 564), and the GPTM Timer B Mode
(GPTMTBMR) register (see page 566). When in one of the concatentated modes, Timer A and Timer
B can only operate in one mode. However, when configured in an individual mode, Timer A and
Timer B can be independently configured in any combination of the individual modes.
11.3.1
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all control
registers are cleared and in their default states. Counters Timer A and Timer B are initialized to all
1s, along with their corresponding load registers: the GPTM Timer A Interval Load (GPTMTAILR)
register (see page 581) and the GPTM Timer B Interval Load (GPTMTBILR) register (see page 582)
and shadow registers: the GPTM Timer A Value (GPTMTAV) register (see page 591) and the GPTM
Timer B Value (GPTMTBV) register (see page 592). The prescale counters are initialized to 0x00:
the GPTM Timer A Prescale (GPTMTAPR) register (see page 585) and the GPTM Timer B Prescale
(GPTMTBPR) register (see page 586).
11.3.2
Timer Modes
This section describes the operation of the various timer modes. When using Timer A and Timer B
in concatenated mode, only the Timer A control and status bits must be used; there is no need to
use Timer B control and status bits. The GPTM is placed into individual/split mode by writing a value
of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 563). In the following sections,
the variable "n" is used in bit field and register names to imply either a Timer A function or a Timer
B function. Throughout this section, the timeout event in down-count mode is 0x0 and in up-count
mode is the value in the GPTM Timer n Interval Load (GPTMTnILR) and the optional GPTM Timer
n Prescale (GPTMTnPR) registers.
11.3.2.1
One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of
the GPTM Timer n Mode (GPTMTnMR) register (see page 564). The timer is configured to count
up or down using the TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register (see page 568), the
timer begins counting up from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit
is set in the GPTMTnMR register, once the TnEN bit is set, the timer waits for a trigger to begin
counting (see the section called “Wait-for-Trigger Mode” on page 553). Table 11-5 on page 551 shows
the values that are loaded into the timer registers when the timer is enabled.
Table 11-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes
Register
TnR
TnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
0x0
0x0
When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start
value from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is
counting up and it reaches the timeout event (the value in the GPTMTnILR and the optional
January 20, 2012
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