LM3S2793 Datasheet, PDF (576/1194 Pages) Texas Instruments – Stellaris® LM3S2793 Microcontroller

General-Purpose Timers
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020
This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in
GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is
set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR.
GPTM Masked Interrupt Status (GPTMMIS)
Timer 0 base: 0x4003.0000
Timer 1 base: 0x4003.1000
Timer 2 base: 0x4003.2000
Timer 3 base: 0x4003.3000
Offset 0x020
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMMIS CBEMIS CBMMIS TBTOMIS
reserved
TAMMIS RTCMIS CAEMIS CAMMIS TATOMIS
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
11
10
Name
reserved
TBMMIS
CBEMIS
Type
RO
RO
RO
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer B Match Masked Interrupt
Value Description
1 An unmasked Timer B Mode Match interrupt
has occurred.
0 A Timer B Mode Match interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
0
GPTM Timer B Capture Mode Event Masked Interrupt
Value Description
1 An unmasked Capture B event interrupt
has occurred.
0 A Capture B event interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
576
January 20, 2012
Texas Instruments-Production Data