LM3S2793 Datasheet, PDF (727/1194 Pages) Texas Instruments – Stellaris® LM3S2793 Microcontroller

Stellaris^® LM3S2793 Microcontroller
Bit/Field
15
14
13:12
11
10
9
Name
CTSEN
RTSEN
reserved
RTS
DTR
RXE
Type
R/W
R/W
RO
R/W
R/W
R/W
Reset
0
0
0
0
0
1
Description
Enable Clear To Send
Value Description
1 CTS hardware flow control is enabled. Data is only transmitted
when the U1CTS signal is asserted.
0 CTS hardware flow control is disabled.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
Enable Request to Send
Value Description
1 RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
0 RTS hardware flow control is disabled.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored
on read.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
Data Terminal Ready
This bit sets the state of the U1DTR output.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
UART Receive Enable
Value Description
1 The receive section of the UART is enabled.
0 The receive section of the UART is disabled.
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
January 20, 2012
727
Texas Instruments-Production Data