LM3S2793 Datasheet, PDF (1088/1194 Pages) Texas Instruments – Stellaris® LM3S2793 Microcontroller

Signal Tables
Table 23-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PD5
I/O
TTL
GPIO port D bit 5.
AIN6
I
Analog Analog-to-digital converter input 6.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
C6
CCP4
I/O
TTL
Capture/Compare/PWM 4.
EPI0S28
I/O
TTL
EPI module 0 signal 28.
I2S0RXMCLK
I/O
TTL
I²S module 0 receive master clock.
U2Rx
I
TTL
UART module 2 receive. When in IrDA mode, this signal has IrDA
modulation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 25-2 on page 1123, regardless of system
implementation.
PH1
I/O
TTL
GPIO port H bit 1.
CCP7
I/O
TTL
Capture/Compare/PWM 7.
C8
EPI0S7
I/O
TTL
EPI module 0 signal 7.
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PH0
I/O
TTL
GPIO port H bit 0.
CCP6
I/O
TTL
Capture/Compare/PWM 6.
C9
EPI0S6
I/O
TTL
EPI module 0 signal 6.
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PG7
I/O
TTL
GPIO port G bit 7.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
C10
EPI0S31
I/O
TTL
EPI module 0 signal 31.
PWM7
O
TTL
PWM 7. This signal is controlled by PWM Generator 3.
PhB1
I
TTL
QEI module 1 phase B.
C11
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C12
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
D2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
D3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 25-6 on page 1128.
PH3
I/O
TTL
GPIO port H bit 3.
EPI0S0
D10
Fault0
I/O
TTL
EPI module 0 signal 0.
I
TTL
PWM Fault 0.
PhB0
I
TTL
QEI module 0 phase B.
1088
Texas Instruments-Production Data
January 20, 2012