LM3S2793 Datasheet, PDF (512/1194 Pages) Texas Instruments – Stellaris® LM3S2793 Microcontroller

External Peripheral Interface (EPI)
Bit/Field
7:6
5:4
3:2
1:0
Name
WRWS
RDWS
reserved
MODE
Type
R/W
R/W
RO
R/W
Reset
0x0
0x0
0x0
0x0
Description
Write Wait States
This field adds wait states to the data phase (the address phase is not
affected). The effect is to delay the rising edge of WRn (or the falling
edge of WR). Each wait state adds 2 EPI clock cycles to the access
time.
Value Description
0x0 Active WRn is 2 EPI clocks.
0x1 Active WRn is 4 EPI clocks.
0x2 Active WRn is 6 EPI clocks.
0x3 Active WRn is 8 EPI clocks.
This field is used in conjunction with the EPIBAUD register.
If both CS0n and CS1n are enabled (the CSCFG field in the EPIHB8CFG2
register is 0x2 or 0x3), the same number of wait states is added to both
CS0n and CS1n accesses.
Read Wait States
This field adds wait states to the data phase (the address phase is not
affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of
RD). Each wait state adds 2 EPI clock cycles to the access time.
Value Description
0x0 Active RDn is 2 EPI clocks.
0x1 Active RDn is 4 EPI clocks.
0x2 Active RDn is 6 EPI clocks.
0x3 Active RDn is 8 EPI clocks.
This field is used in conjunction with the EPIBAUD register
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Host Bus Sub-Mode
This field determines which of four Host Bus 8 sub-modes to use.
Sub-mode use is determined by the connected external peripheral. See
Table 10-5 on page 486 for information on how this bit field affects the
operation of the EPI signals.
Value Description
0x0 ADMUX – AD[7:0]
Data and Address are muxed.
0x1 ADNONMUX – D[7:0]
Data and address are separate.
0x2 Continuous Read - D[7:0]
This mode is the same as ADNONMUX, but uses address switch
for multiple reads instead of OEn strobing.
0x3 XFIFO – D[7:0]
This mode adds XFIFO controls with sense of XFIFO full and
XFIFO empty. This mode uses no address or ALE.
512
January 20, 2012
Texas Instruments-Production Data