TLC320V343 Datasheet, PDF (8/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
SLAS159 – MARCH 1997
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
Positive supply voltage, VDD
Steady-state differential voltage between any two supplies
4.5
5 5.5 V
0.1 V
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Load current from ADC VMID and DAC, IO
Conversion time for the ADC and DAC channels
2.2
V
0.8 V
100 µA
10 FCLK periods
Master clock frequency, fMCLK
Analog input voltage (differential, peak to peak), VID(PP)
10.368
6
15 MHz
V
Differential output load resistance, RL
Single ended to buffered DAC VMID voltage load resistance, RL
600
Ω
300
Operating free-air temperature, TA
0
70 °C
NOTE: 2. To avoid possible damage to these CMOS devices and associated operating parameters, the sequence below must be followed when
applying power:
(1) Connect SUBS, DGTL GND, ADC GND, and DAC GND to ground.
(2) Connect voltages ADC VDD and DAC VDD.
(3) Connect voltage DGTL VDD.
(4) Connect the input signals.
The sequence below must be followed when removing power.
(1) Disconnect the input signals.
(2) Disconnect voltage DGTL VDD.
(3) Disconnect voltages ADC VDD and DAC VDD.
(4) Disconnect SUBS, DGTL GND, ADC GND, and DAC GND from ground.
electrical characteristics over recommended range of operating free-air temperature,
MCLK = 5.184 MHz, V_DD = 5 V, outputs unloaded, for total device
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
IDD
Supply
current
PWR DWN = 1 and clock signals present
PWR DWN = 0 after 500 µs and clock signals present
20
22
1
2
PWR DWN = 1 and clock signals present
100
PD
Power
PWR DWN = 0 after 500 µs and clock signals present
dissipation _{Software power down, (bit D00,}
register 6 set to 1)
5
15
20
ADC VMID
No load
ADC VDD/2
– 0.1
ADC VDD/2
+ 0.1
DAC VMID
No load
† _{All typical values are at VDD = 5 V and TA = 25°C.}
DAC VDD/2
– 0.1
DAC VDD/2
+ 0.1
UNIT
mA
mA
mW
mW
mW
V
V
8
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