TLC320V343 Datasheet, PDF (13/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
SLAS159 – MARCH 1997
monitor output characteristics, V_DD = 5 V (unless otherwise noted) (see Note 20)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VO(PP) Peak-to-peak ac output voltage
Quiescent level = ADC VMID
ZL = 10 kΩ and 60 pF
1.3
1.5
V
VOO Output offset voltage
No load, single ended
relative to ADC VMID
5
10 mV
ro
VOC
DC output resistance
Output common-mode voltage
No load
50
Ω
0.4 ADC 0.5 ADC 0.6 ADC
VDD
VDD
VDD
V
Gain = 0 dB
– 0.2
0
0.2
G
Voltage gain (see Note 21)
Gain 2 = – 8 dB
Gain 3 = – 18 dB
– 8.2
– 18.4
–8
– 7.8
dB
– 18 – 17.6
Squelch (see Note 22)
– 60
NOTES: 20. All monitor output tests are performed with a 10-kΩ load resistance.
21. Monitor gains are measured with a 1020-Hz, 6-V peak-to-peak sine wave applied differentially between IN + and IN –.The monitor
output gains are nominally 0 dB, – 8 dB, and – 18 dB relative to its input; however, the output gains are – 6 dB relative to IN + and
IN – or AUX IN + and AUX IN –.
22. Squelch is measured differentially with respect to ADC VMID.
timing requirements and specifications in master mode
recommended input timing requirements for master mode, V_DD = 5 V
tr(MCLK)
tf(MCLK)
tw(RESET)
tsu(DIN)
th(DIN)
Master clock rise time
Master clock fall time
Master clock duty cycle
RESET pulse duration
DIN setup time before SCLK low (see Figure 3)
DIN hold time after SCLK high (see Figure 3)
MIN
40%
1 MCLK
25
NOM
5
5
MAX
60%
20
UNIT
ns
ns
ns
ns
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