TLC320V343 Datasheet, PDF (4/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
SLAS159 – MARCH 1997
Terminal Functions (Continued)
TERMINAL
NAME
NO.† NO.‡ ^I/O
DESCRIPTION
FS
12
4 I/O Frame synchronization. When FS goes low, DIN begins receiving data bits and DOUT begins
transmitting data bits. In master mode, FS is low during the simultaneous 16-bit transmission to DIN
and from DOUT. In slave mode, FS is externally generated and must be low for one shift-clock period
minimum to initiate the data transfer.
FSD
17
14
O Frame synchronization delayed output. This FSD active-low output synchronizes a slave device to
the frame synchronization timing of the master device. FSD is applied to the slave FS input and is
the same duration as the master FS signal but delayed in time by the number of shift clocks
programmed in the FSD register.
IN +
26
36
I Noninverting input to analog input amplifier
IN –
25
35
I Inverting input to analog input amplifier
MCLK
14
10
I The master clock input drives all of the key logic signals of the AIC.
MON OUT
1
40
O The monitor output allows monitoring of analog input and is a high-impedance output.
M/S
18
16
I Master/slave select input. When M/S is high, the device is the master and when low, it is a slave.
OUT+
OUT–
3
43
O Noninverting output of analog output power amplifier. OUT+ can drive transformer hybrids or
high-impedance loads directly in a differential connection or a single-ended configuration with a
buffered VMID.
4
46
O Inverting output of analog output power amplifier. OUT– is functionally identical with and
complementary to OUT+.
PWR DWN
2
42
I Power-down input. When PWR DWN is taken low, the device is powered down so that the existing
internally programmed state is maintained. When PWR DWN is brought high, full operation resumes.
RESET
8
57
I Reset input that initializes the internal counters and control registers. RESET initiates the serial data
communications, initializes all of the registers to their default values, and puts the device in a
preprogrammed state. After a low-going pulse on RESET, the device registers are initialized to
provide a 16-kHz data conversion rate and 7.2-kHz filter bandwidth for a 10.368-MHz master clock
input signal.
SCLK
13
8 I/O Shift clock. SCLK clocks the digital data into DIN and out of DOUT during the frame synchronization
interval. When configured as an output (M/S high), SCLK is generated internally by dividing the
master clock signal frequency by four. When configured as an input (M/S low), SCLK is generated
externally and synchronously to the master clock. This signal clocks the serial data into and out of
the device.
SUBS
21
24
I Substrate connection. SUBS should be tied to ADC GND.
† _{Terminal numbers shown are for the FN package.}
‡ _{Terminal numbers shown are for the PM package.}
4
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