TLC320V343 Datasheet, PDF (14/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
SLAS159 – MARCH 1997
operating characteristics over recommended range of operating free-air temperature, V_DD = 5 V (unless
otherwise noted) (see Note 23)
PARAMETER
MIN
tf(SCLK)
tr(SCLK)
Shift clock fall time (see Figure 3 )
Shift clock rise time (see Figure 3)
Shift clock duty cycle
45%
td(CH-FL)
Delay time from SCLK high to FS low
(see Figure 3, Figure 5, and Note 24)
td(CH-FH)
td(CH-DOUT)
Delay time from SCLK high to FS high (see Figure 3)
Delay time from SCLK high to DOUT valid
(see Figure 3 and Figure 8)
td(CH-DOUTZ) Delay time from SCLK↑ to DOUT in high-impedance state (see Figure 9)
td(ML-EL)
Delay time from MCLK low to EOC low (see Figure 10)
td(ML-EH)
Delay time from MCLK low to EOC high (see Figure 10)
tf(EL)
EOC fall time (see Figure 10)
tr(EH)
EOC rise time (see Figure 10)
td(MH-CH)
Delay time from MCLK high to SCLK high
td(MH-CL)
Delay time from MCLK high to SCLK low
td(MH-FL)
Delay time from MCLK high to FS low
NOTES: 23. All timing specifications are valid with CL = 20 pF.
24. FSD occurs 1/2 shift-clock cycle ahead of FS when the device is operating in the master mode.
TYP MAX UNIT
13
18 ns
13
18 ns
55%
5
15 ns
5
20 ns
20 ns
20
ns
40
ns
40
ns
13
ns
13
ns
50 ns
50 ns
53 ns
14
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