TLC320V343 Datasheet, PDF (5/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
SLAS159 – MARCH 1997
detailed description
definitions and terminology
ADC channel
d
Dxx
DAC channel
Data transfer
interval
DSxx
f_i
Frame sync
Frame sync and
sampling period
Frame-sync
interval
f_s
Host
Primary (serial)
communications
Secondary (serial)
communications
Signal data
All signal processing circuits between the analog input and the digital conversion results
at DOUT
Valid programmed or default data in the control register format (see secondary serial
communications definition) when discussing other data-bit portions of the register
Bit position in the primary data word (xx is the bit number)
All signal processing circuits between the digital data word applied to DIN and the
differential output analog signal available at OUT+ and OUT–
The time during which data is transferred from DOUT and to DIN. This interval is 16 shift
clocks regardless of whether the shift clock is internally or externally generated. The
data transfer is initiated by the falling edge of the frame-sync signal.
Bit position in the secondary data word (xx is the bit number)
The analog input frequency of interest
The falling edge of the signal that initiates the data-transfer interval. The primary frame
sync starts the primary communications, and the secondary frame sync starts the
secondary communications.
The time between falling edges of successive primary frame-sync signals
The time period occupied by 16 shift clocks. Regardless of the mode of operation, there
is always an internal frame-sync interval signal that goes low on the rising edge of SCLK
and remains low for 16 shift clocks. It is used for synchronization of the serial-port
internal signals. It goes high on the seventeenth rising edge of SCLK.
The sampling frequency that is the reciprocal of the sampling period
Any processing system that interfaces to DIN, DOUT, SCLK, or FS
The digital data-transfer interval. Since the device is synchronous, the signal data words
from the ADC channel and to the DAC channel occur simultaneously.
The digital control and configuration data-transfer interval into DIN, and the register
read-data cycle out DOUT. The data-transfer interval occurs when requested by
hardware or software.
The input signal and all of the converted representations through the ADC channel which
returns through the DAC channel to the analog output. This is contrasted with the purely
digital software control data.
ADC signal channel
To produce excellent common-mode rejection of unwanted signals, the analog signal is processed differentially
until it is converted to digital data. The signal is amplified by the input amplifier at one of three software-selectable
gains (typically 0 dB, 6 dB, or 12 dB). A squelch mode can also be programmed for the input amplifier.
The amplifier output is filtered and applied to the ADC input. The ADC converts the signal into discrete digital
words in 2s-complement format corresponding to the analog-signal value at the sampling time. These 16-bit
digital words, representing sampled values of the analog input signal, are clocked out of the serial port, (DOUT),
one word for each primary communication interval. During secondary communications, the data previously
programmed into the registers can be read out with the appropriate register address and with the read bit set
to 1. When no register read is requested, all 16 bits are 0.
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