TLC320V343 Datasheet, PDF (17/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
PARAMETER MEASUREMENT INFORMATION
SLAS159 – MARCH 1997
2V
SCLK
FS† _{0.8 V}
tf(SCLK)
2V
0.8 V
td(CH-FL)
DOUT‡
D15
D14
D13
tr(SCLK)
td(CH-DOUT)
D12
D11
2V
td(CH-FH)
2V
D2
D1
D0
tsu(DIN)
DIN
D15
D14
D13
D12
D11
th(DIN)
D2
D1
D0
† _{The time between falling edges of two primary FS signals is the conversion period.}
‡ _{The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling edge}
of the shift clock.
Figure 3. AIC Stand-Alone and Master-Mode Timing
SCLK ^{2 V}
§
FS†
DOUT‡
D15
tf(SCLK)
2V
0.8 V
tr(SCLK)
td(CH-DOUT)
D14
D13
D12
D11
tc(SCLK)
2V
2V
D2
D1
D0
tsu(DIN)
DIN
D15
D14
D13
D12
D11
D2
D1
D0
th(DIN)
† _{The time between falling edges of two primary FS signals is the conversion period.}
‡ _{The data on DOUT are shifted out on the rising edge of the shift clock, and the data on DIN are shifted in on the falling edge}
of the shift clock.
§ _{The high-to-low transition of FS must must occur within ±1/4 of a shift-clock period around the 2-V level of the shift clock.}
Figure 4. AIC Slave and Codec Emulation Mode
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