TLC320V343 Datasheet, PDF (15/30 Pages) Texas Instruments – SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT

TLC320V343
SINGLE-SUPPLY ANALOG INTERFACE CIRCUIT
SLAS159 – MARCH 1997
timing requirements and specifications in slave mode and codec emulation mode
recommended input timing requirements for slave mode, V_DD = 5 V
tr(MCLK)
tf(MCLK)
tw(RESET)
tsu(DIN)
th(DIN)
tsu(FL-CH)
Master clock rise time
Master clock fall time
Master clock duty cycle
RESET pulse duration
DIN setup time before SCLK low (see Figure 4)
DIN hold time after SCLK high (see Figure 4)
Setup time from FS low to SCLK high
MIN
40%
1 MCLK
20
NOM
5
5
MAX
60%
20
± SCLK/4
UNIT
ns
ns
ns
ns
ns
operating characteristics over recommended range of operating free-air temperature, V_DD = 5 V (unless
otherwise noted) (see Note 23)
PARAMETER
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock cycle time (see Figure 4)
Shift clock fall time (see Figure 4)
Shift clock rise time (see Figure 4)
Shift clock duty cycle
td(CH-FDL)
td(CH-FDH)
td(FL-FDL)
Delay time from SCLK high to FSD low (see Figure 7)
Delay time from SCLK high to FSD high
Delay time from FS low to FSD low (slave to slave) (see Figure 6)
td(CH-DOUT) Delay time from SCLK high to DOUT valid (see Figure 4 and Figure 8)
td(CH-DOUTZ) Delay time from SCLK↑ to DOUT in high-impedance state (see Figure 9)
td(ML-EL)
Delay time from MCLK low to EOC low (see Figure 10)
td(ML-EH)
Delay time from MCLK low to EOC high (see Figure 10)
tf(EL)
EOC fall time (see Figure 10)
tr(EH)
EOC rise time (see Figure 10)
td(MH-CH)
Delay time from MCLK high to SCLK high
td(MH-CL)
Delay time from MCLK high to SCLK low
NOTE 23: All timing specifications are valid with CL = 20 pF.
MIN
125
45%
TYP MAX UNIT
ns
18 ns
18 ns
55%
50 ns
40 ns
40 ns
40 ns
20
ns
40
ns
40
ns
13
ns
13
ns
50 ns
50 ns
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