THS788 Datasheet, PDF (8/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
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THS788 CIRCUIT FEATURES
The THS788 time-measurement unit (TMU) includes four measurement channels plus a synchronization channel
optimized to make high-accuracy time-interval measurements. The following is a brief description of the various
circuit blocks and how they interact to make and process the time measurements.
Counter, Latches, Clock Multiplier
The center of the TMU is a master synchronous counter which counts continuously at a rate of 1.2 GHz. This is
the master timing generator for the whole TMU and defines the basic timing interval of 833 ps, which is further
subdivided with Interpolator circuitry. The counter is divided into four sections, which can be powered off so that
the effective length is selectable as 18, 27, or 34 bits long. The output bits of the counter are connected to five
sets of latches, which can latch and hold the counter state on command from each of the channels. In this way,
when an event occurs, the counter time is recorded in the particular channel’s latches. The latch output is
converted to CMOS levels and passed to the respective channel’s FIFO buffer, which is 15 samples deep. The
counter 1.2-GHz clock is derived from the MCLK input to the TMU at 200 MHz. This MCLK input is critical to the
accuracy of the TMU, and any error in frequency is reflected as errors in time measurement. Likewise, jitter
propagates to the counter and other circuits and adds noise to the measurement accuracy. The 200-MHz clock is
the input to a clock multiplier. The clock multiplier uses delay-lock loop (DLL) techniques and combinatorial logic
to construct a six-times clock from the reference input. This 1.2-GHz clock is passed to a high-power clock
buffer, which drives all the circuitry in the master counter and many other circuits in the TMU.
Channels, Interpolator, Preconditioning
There are four event channels and one sync channel. The event channels are identical, and the sync channel
contains most of the event channel circuitry, but without a FIFO and preconditioning. An input pulse to the sync
channel serves as the reference time zero for the TMU. An event input to a channel is compared to the sync time
reference, and the time delay is calculated as the time difference modified by a calibration value. An event input
follows the following signal path: the event input edge sets a fast latch (hit latch). This latch is gated on/off by a
block of preconditioning logic which can set up holdoff delay conditions to determine when to allow the latch to
accept an event pulse. This document discusses holdoff preconditioning in more complete detail in later sections.
The output of the latch is current-buffered and applied to the interpolator. The interpolator uses DLL techniques
to subdivide the counter interval of 833 ps into 64 time intervals of 13 ps each. A large array of fast latches
triggered by the hit latch captures the state of the 64 time intervals and logically determines 6 bits of timing data
based on where the event occurred in the 833-ps clock interval. These 6 bits are latched and eventually passed
to the FIFO, where they become the LSBs of the time-to-data conversion. A synchronizer circuit is also
connected to the 64-latch array and removes the possible timing ambiguity between the 64 latches and the
master counter. This takes a few 1.2-GHz clock pulses. When this process is complete, a pulse occurs which
captures the master counter bits into the channel latches. A subsequent pulse loads all the bits from the
interpolator and the counter into the channel FIFO. While this is happening, the hit latch is being reset, and the
channel is prepared to accept another event edge. This process is fast enough to accept and measure event
edges as close together as 5 ns.
FIFO
Each event channel contains a 15-deep, 40-bit-wide FIFO, which allows for rapid accepting and measurement of
event inputs and a user-defined data-output rate of those measurements.
Calibration, ALU, Tag, Shifter
The output of the FIFO is controlled by the shifter, which is a free-running parallel-to-serial register. The shifter bit
length and clock rate are user controlled. The shifter generates a load pulse, which transfers the data in the FIFO
output into an arithmetic logic unit, which does the sync time and calibration time subtractions and then
parallel-loads the result into the output serial register. An LVDS output buffer outputs the clock, data, and strobe
signals to transfer the time-measurement data to the user. A TAG bit is appended to the leading edge of the data
word. Currently the TAG feature is not implemented. The bit will always be 0 representing data.
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