THS788 Datasheet, PDF (10/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
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Reset places the TMU in a predetermined idle state at power on, and anytime the system software initializes the
system hardware. In the idle state, the TMU ignores state changes on the Event inputs and never creates time
stamps. The TMU is capable of switching within 250 μs from the idle state to a state that creates accurate time
stamps.
Chip ID
Address (83h) is a read-only register that identifies the product and the die revision. The 16-bit register is divided
into two 8-bit sections. The LSB represents the revision history and the MSB represents the last two digits of
THS788 (i.e., 80). The first revision (1.0) is as follows:
1000 0000 0001.0000
Read Operations
Reading the THS788 registers via the host interface requires the following sequence:
The host controller initiates a read cycle by setting the host strobe signal, Hstrobe, to a low state. The serial
Hdata sequence starts with a high R/W bit, followed by (either 1 or 0) for parallel-write bit and 8 bits of address,
with most-significant bit (A7) first. The host controller should put the Hdata signal in the high-impedance state
beginning at the falling edge of HCLK pulse 10. The THS788 allows one clock cycle, (r) for the host to reverse
the data-channel direction and begins driving the Hdata line on the falling edge of HCLK pulse 12. The data is
read beginning with the most-significant bit (D15) and ending with the least-significant bit (D0).
The host must drive Hstrobe to a high state for a minimum of two HCLK periods beginning at the falling edge of
HCLK pulse 27 to indicate the completion of the read cycle. Figure 3 shows the timing diagram of the read
operation.
Hstrobe
HCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
27 28 29
Hdata
R₁ /W X A7 A6 A5 A4 A3 A2 A1 A0 r0 D15 D14 D13 D12 D11 D10 D9
Register Address (A7:A0)
Data Out
Data transfer protocol for Read operations
Hdata becomes output
Driving the line
Figure 3. Read Operation
D0 X X R/W
T0427-01
Write Operations
Writing into the THS788 registers via the host interface requires the following sequence:
After the Hstrobe line is pulled low (start condition), the R/W bit is set low, followed by a 0 for the parallel-write bit
(single-register write), then the memory address (A7–A0) followed by the data (D15:D0) to be programmed. The
next clock cycle (w) is required to allow data to be latched and stored at the destination address (or addresses in
the case of a parallel write), followed by at least two dummy clock cycles during which the Hstrobe is high,
indicating the completion of the write cycle. Figure 4 and Figure 5 show timing diagrams of write operations.
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