THS788 Datasheet, PDF (33/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

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THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
SYNC
SYNC_TS_Pol = 0
Pol_X = 1
SYNC
SYNC_TS_Pol = 1
Pol_X = 0
EVENT
EVENT
T1
T2
T3
T1
SYNC
SYNC_TS_Pol = 1
Pol_X = 1
EVENT
T1
T2
Figure 14. Time Measurement Examples With Different Edge Polarities
T0431-01
Output Clock to Data/Strobe Phasing
The output of each channel is an Rdata and Rstrobe signal. The RCLK for all the channels is a common
output. At the higher output clock rates, these signals must be handled carefully. Particularly important are
the termination and phase alignment of the signals at the receiving circuitry. Termination has been discussed
previously. Phase alignment is now discussed: The two outputs from each channel are clocked out through
identical flip-flops with the same internal clock. Data and strobe output edges from a particular channel match
well (< 50 pS). The match channel-to-channel is not as good due to the greater wiring distances internal to
the TMU. However, the total time difference is below 125 pS. Because the RClock is a common output, the
wiring lengths from the four channels must be matched and controlled to achieve good setup and hold times
at the input to the receiving circuit. The RClock rising edge is adjusted internal to the TMU to be close to the
center of the eye diagram of the data/strobe signals. This is true for all four output frequencies. (The internal
clock has a good 50/50 duty cycle. The rising edge clocks out the data/strobe. The falling edge is inverted
and used as the RClock after appropriate adjustments for the internal propagation delay times.) The DDR
clock is similarly adjusted in time to put both edges close to the center of the data/strobe outputs. The
receiving circuitry requirements for setup and hold timing must be carefully examined for the proper timing.
Delays may be added to the PCB microstrips to adjust timing. A good rule is 125 ps of delay per inch of
microstrip length.
Master Clock Input and Clock Multiplier
All of the internal timing of the TMU is derived from the 200-MHz master clock. Therefore, its quality is critical to
the accurate operation of the TMU. Absolute accuracy of the master clock linearly affects the accuracy of the
measurements. This imposes little burden upon the master clock, as accurate oscillators are easy to procure or
distribute. However, the jitter of the master clock is also highly critical to the single-event precision of the TMU
and should be absolutely minimized (<3 ps rms). A carefully selected crystal oscillator can meet this requirement.
However, jitter can build up quite quickly in a clock distribution scheme and must be carefully controlled. Be
careful that the LVDS input to the master clock is not badly distorted or that the rise/fall times are slow (>.6 ns).
Discussion of the clock multiplier follows: The TMU operates from a master-clock frequency of 1200 MHz, which
implies a measurement period of 0.833 ns. The master counter runs from this frequency, and all the other clocks
are divided down from this main clock. An interpolator allows finer precision in time measurement, as discussed
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