THS788 Datasheet, PDF (28/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
www.ti.com
All the programming to the THS788 is achieved through an LVCMOS host-serial interface. With this interface, the
user has the ability to set up the THS788 for time measurements. It also provides the user with different modes
to retrieve the results.
Results are available through an LVDS-compatible high-speed serial interface. Data-word length and speed are
programmable to cover a wide range of data rates. Each channel has it own output to maximize data throughput.
All of the data ports (RdataA, -B, -C, and -D) are synchronized to a global clock.
LVDS-COMPATIBLE I/Os
The Event, SYNC, and master-clock inputs are LVDS-compatible input receivers optimized for high-speed and
low-time-distortion operation. The Rdata, Rstrobe, and RCLK outputs are similarly LVDS-compatible output
drivers optimized for high-speed/low-distortion operation, driving 50-Ω transmission lines. Typically, LVDS data
transmission is thought of in terms of 100-Ω twisted-wire-pair (TWP) transmission lines. TWP is not applicable to
printed wiring boards and high-speed operation. Therefore, the THS788 interfaces were designed to operate
most effectively with 50-Ω, single-ended transmission lines. Instead of a current-mode output with its
correspondingly high output impedance, a more-nearly impedance-matched voltage-mode output driver is used.
This minimizes reflections from mismatched transmission line terminations and the resulting waveform distortion.
The input receivers do not include the 100-Ω terminating resistor, which must be connected externally to the
THS788. This was done to accommodate daisy-chaining the THS788 inputs. Input offset voltage was minimized,
and the fail-safe feature in the LVDS standard was eliminated in order to minimize distortion.
LVDS-COMPATIBLE INPUTS
The four event inputs, the sync input and the master-clock input all use the same input interface circuitry.
Figure 9 is a simplified schematic diagram of the LVDS-compatible receiver input stage. The input signal is
impedance-transformed and level-shifted with a PNP emitter-follower and translated into ECL-like differential
signals with a common-emitter amplifier. There is no internal termination resistor and no internal pullup/pulldown
resistors. Unused inputs may be tied off by connecting both input terminals to ground. If the input terminals are
left floating, they are protected by ESD clamps from damage; however, noise may be injected into the THS788
and may degrade accuracy. The peak input voltage limits are 0.6 V to 1.7 V. Outside of these limiting voltages,
parts of the input circuit may saturate and distort the timing.
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