THS788 Datasheet, PDF (25/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

www.ti.com
THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
Rstrobe
RCLK
Rdata
00
TAG
0 R0 R1 R2 R3 R4 R5
R10 R11 R12 R13 R14 R15 0 0 0 R0 R1 R2 R3 R4 R5 R6 R7
Result Data
Sign bit when
programmed
Cycle
End
New Cycle
T0455-01
Figure 7. Result-Interface Operation B
Note: In the preceding diagrams, only RCLK_P is drawn in order to indicate the correct edge with respect to
data.
DDR Mode
The result interface may be operated using one-half the clock frequency while keeping the data bit rate
unchanged. In this mode, data is clocked out of the device using both edges of RCLK. A register bit (DDR_EN) is
used to enable DDR mode.
Result-Interface Clock
The result-interface clock (RCLK) is generated internally and runs at a maximum frequency of 300 MHz. RCLK is
programmable and may be programmed using two register bits (RCLK_sel0 and RCLK_sel1) according to the
following table:
RCLK Frequency (MHz)
Normal Mode
75 (default)
150
300
Table 21. Result-Interface Clock
RCLK Frequency (MHz)
DDR Mode
37.5
75
150
RCLK_sel1
0
0
1
RCLK_sel0
0
1
0
Output Interface Throughput
Multiple data-word lengths and bit speeds, combined with a 15-sample-deep FIFO, give exceptional flexibility to
output data throughput. The actual throughput is easily calculated, keeping in mind the following: The selected
word length includes N – 1 data bits and 1 sign bit, which are sent out last as the MSB. Two bit times do not
have meaningful data during the Rstrobe high time. The TAG bit is appended to the data bits and is sent first.
Example: for a bit rate of 300 MB/s and 16-bit length, the bit time is 3.33 ns, and the total word length is 16 + 1 +
2 = 19 bit times. Therefore, the throughput is 15.8 M samples/s. This is a constant output sample rate. The TMU
can take time measurements at up to 200 MS/s. The 15-deep FIFO buffers these two rates until it is filled, in
which case samples are lost.
Serial Results Latency
The event stored in the FIFO will be transferred to ALU and subsequently to the free running results data shift
register when the shift register enters a load pulse. The load pulse is generated once per ALU/shift register
processing cycle. The load pulse will trigger the ALU and transfer result to the parallel to serial shift register for
output. The cycle time of the load pulse is dependent upon the depth of the result transfer register and data rate.
Since the results parallel to serial register is free running, the load pulse will be asynchronous to the actual event.
So, the latency will depend upon where in the current cycle the load pulse occurred relative to the event being
captured into the FIFO.
Copyright © 2010–2011, Texas Instruments Incorporated
25