THS788 Datasheet, PDF (24/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
www.ti.com
Serial-Results Interface
The TMU captures time-stamp results and sends them to external logic using an LVDS serial-results port. The
serial-results port consists of a clock signal (RCLK), four strobe signals (Rstrobex) and four data signals
(Rdatax). The Rstrobex signal indicates that a time-stamp data transfer is about to begin for the corresponding
channel.
The serial-result interface can be programmed to have a variable data-length format. Three register bits
(Rlength0, Rlength1, and Rlength2), are used to program the required data transfer formats.
The default length of the data field is 40 bits, and it is in 2s-complement format. The following table defines the
various data formats:
Table 20. Result Transfer Format and Time Range
RESULT TRANSFER FORMAT
8 bits
16 bits
24 bits
32 bits
40 bits
TIME RANGE
-1.653 ns to 1.667 ns
-426.626 ns to 426.639 ns
-109.22 µs to 109.22 μs
-27.96 ms to 27.96 ms
-7.158 s to 7.158 s
Rlength2
0
0
0
0
1
Rlength1
0
0
1
1
0
Rlength0
0
1
0
1
0
Note that the previous table refers to the 2s-complement format. Therefore, the 8-bit result represents a number
between –127 and 128.
Result-Interface Operation
The TMU initiates a read cycle by setting the strobe signal, Rstrobe, to a low state, indicating that the data
transfer is about to begin. The serial Rdata sequence starts with a TAG bit, followed by the 40-bit data (R0 to
R39). R39 (MSB) is the sign bit. Following the last data bit (R39), the strobe signal (Rstrobe) goes high for two
clock cycles, indicating the end of the transaction.
The data is clocked out of the TMU on the rising edge of RCLK. The receiving device clocks the data in on the
rising edge of RCLK. Figure 6 shows a 40-bit result on the result interface. Figure 7 shows a 16-bit result on the
result interface.
Rstrobe
RCLK
Rdata
0 0 0 R0 R1 R2 R3 R4 R5
R34 R35 R36 R37 R38 R39 0 0 0 R0 R1 R2 R3 R4 R5 R6 R7
TAG
TAG = 0, Valid Data
Result Data
Sign bit when
programmed
Cycle
End
New Cycle
T0428-01
Figure 6. Result-Interface Operation A
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