THS788 Datasheet, PDF (21/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

THS788
www.ti.com
SLOS616B – MARCH 2010 – REVISED JUNE 2011
Event Latches
Each event channel and the sync channel include two event latches whose inputs are both connected to the
LVDS input-buffer output. One latch is the time-measurement signal path and connects to the interpolator and
synchronizer. The other latch connects to the preconditioning circuitry. A selectable rising or falling edge of an
event pulse sets the latch. the latch remains set until the interpolator has finished processing the event, at which
time the interpolator resets the latch. The latch, however, does not accept another event pulse until the event
input returns to its initial state and remains for the initial event-pulse duration. Any event transitions which occur
before the interpolator has completed processing the previous event are ignored. For example, assume that
rising edge is selected. Two rising edges can occur as quickly as 5 ns apart. The falling edge can occur
anywhere from 250 ps after the rising edge to 250 ps before the next rising edge. Any other edges or glitches are
ignored. In addition to the rising/falling-edge selection, the event latch includes the gating function whereby the
preconditioning logic controls whether the TMU accepts and processes an event input. The second event latch
operates similarly to the main signal-path latch with the following exceptions: The latch is followed by and
ECL-to-CMOS converter , because all the preconditioning logic is CMOS instead of the fast ECL circuitry in the
measurement chain. The preconditioning logic rather than the interpolator resets this latch, and the timing of the
reset pulse is slightly faster than the interpolator.
Preconditioning Holdoff Delay Time
The preconditioning circuitry controls the ON/OFF state of the event latches. Following a Sync input signal, the
TMU checks for a number of conditions before it proceeds with the time-measurement operation. Event input
signals are ignored until all arming conditions are met. These conditions are as follows:
The hold-off delay is a programmable delay used to inhibit the creation of the next time stamp until the hold-off
delay has expired. A 16-bit register is used for the hold-off delay count register. One holdoff delay register exists
for each of the four event input channels.
The generation of a time stamp reloads the value from the holdoff delay register into a down counting counter.
Time stamp generation pauses until hold-off delay counter reaches zero. There are seven ranges for the holdoff
delay maximum duration. Three register bits are used to specify the required range.
The following table defines these ranges:
Range
1
2
3
4
5
6
7
HOffRng2_x
0
0
0
0
1
1
1
Table 15. Preconditioning Holdoff Delay Time
HOffRng1_x
0
0
1
1
0
0
1
HOffRng0_x
0
1
0
1
0
1
X
Full Range (ms)
0.655
2.621
10.486
41.943
167.772
671.089
2,684
LSB (ns)
10
40
160
640
2560
10,240
40,960
In range 1 each count in the holdoff register delays the next possible time stamps by 10 ns (100-MHz clock
period). The maximum delay range for this feature is 2.684 s for each channel. To disable this feature, a register
bit (HOffTm_EN_x) is set to 0.
Arming Conditions
An additional arming condition for each event channel is based on other channels meeting some preprogrammed
conditions before it can become fully armed. These conditions are in addition to the individual channel arming
conditions.
• A given channel does not become fully armed until one, two, or all three of the other channels are armed. A
logical AND of one or more channels.
• A given channel does not become fully armed until the holdoff delay expires, the arming counter reaches
zero, and the logical OR of one or more channels has been active.
The following tables define this conditional operation.
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