THS788 Datasheet, PDF (34/43 Pages) Texas Instruments – QUAD-CHANNEL TIME MEASUREMENT UNIT (TMU)

THS788
SLOS616B – MARCH 2010 – REVISED JUNE 2011
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elsewhere. The clock multiplier is the circuit that takes the 200-MHz master-clock reference and generates from
that the high quality 1200-MHz clock. The clock multiplier consists of five major sections: First is the delay-lock
loop (DLL), which is a series connection of 12 identical and closely matched variable time-delay circuits. A single
control voltage connects to each of the delay elements. The master 200-MHz clock connects to the input of the
DLL. Because the period of 200 MHz is 5 ns, if the control voltage is adjusted to make the time delay of the DLL
equal to 5 ns, the input and the output of the delay line is exactly phase matched. A phase detector connected to
the input and the output of the delay line can sense this condition accurately, and a feedback loop with a
low-offset-error amplifier is included in the clock multiplier to achieve this result. These are the second and third
circuit blocks. With 12 equally spaced 200-MHz clock phases, select out six equally spaced 833-ps-wide pulses
with AND gates and combine these pulses into a single 1200-MHz clock waveform with a six-input OR gate. The
last circuit element is a powerful differential signal buffer to distribute the 1200-MHz clock to the various circuit
elements in the TMU. The DLL feedback loop is fairly narrowband, so some time is required to allow the DLL to
initialize at start-up (about 100 μs, typical). The DLL is insensitive to the duty cycle of the input 200-MHz clock.
Duty cycles of 40/60 to 60/40 are acceptable. What matters most is as little jitter as possible. See Figure 16 for
typical sigmas across the 200-MHz master clock 5-ns window. Data in figure represents asynchronous master
clock and sync/events. Sigmas vary across the window primarily based on probabilities of one or both of the
sync/events being impacted from 200-MHz switching noise.
Figure 15. Typical per Channel Sigmas
vs
5-ns (200-MHz) Window
9
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7
6
5
4
3
0
1
2
3
4
5
6
Sync to Event Delay (ns)
Figure 16.
Temperature Measurement and Alarm Circuit
Chip temperature of the TMU is monitored by a temperature sensor located near the center of the chip. A small
buffer outputs a voltage proportional to the absolute temperature of the TMU. The buffer drives a load of up to
100 pF typical (50 pF minimum) and open circuit to 10 kΩ to ground resistive. The output voltage slope is 5 mV,
typical. Therefore, the output voltage equation is as follows:
Output Voltage = (Temperature in degrees C × 5 mV) + 1.365 V
(5)
Also included in the TMU is an overtemperature comparator. At approximately 140°C, the alarm goes active, and
at approximately 7°C below this temperature, the alarm becomes inactive (hysteresis of 7°C prevents tripping on
noise and comparator oscillations). If the alarm goes active, the chip powers down and sets a bit in the serial
register.
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