MSP430FR5989-EP Datasheet, PDF (8/154 Pages) Texas Instruments – Mixed-Signal Microcontroller

MSP430FR5989-EP
SLASEC9 – APRIL 2017
www.ti.com
Table 3-1. Signal Descriptions – MSP430FR5989-EP (continued)
TERMINAL
NAME
RGC
NO.
General-purpose digital I/O
DESCRIPTION
P3.5/UCA1SOMI/UCA1RXD/TB0.1
USCI_A1: Slave out, master in (SPI mode)
27
USCI_A1: Receive data (UART mode)
Timer_B TB0 CCR1 capture: CCI1A input, compare: Out1 output
General-purpose digital I/O
P3.6/UCA1CLK/TB0.2
28 USCI_A1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
Timer_B TB0 CCR2 capture: CCI2A input, compare: Out2 output
General-purpose digital I/O
P3.7/UCA1STE/TB0.3
29 USCI_A1: Slave transmit enable (SPI mode)
Timer_B TB0 CCR3 capture: CCI3B input, compare: Out3 output
General-purpose digital I/O
P2.3/UCA0STE/TB0OUTH
30 USCI_A0: Slave transmit enable (SPI mode)
Switch all PWM outputs high impedance input - Timer_B TB0
General-purpose digital I/O
P2.2/UCA0CLK/TB0.4/RTCCLK
USCI_A0: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
31
Timer_B TB0 CCR4 capture: CCI4B input, compare: Out4 output
RTC clock output for calibration
General-purpose digital I/O
USCI_A0: Slave out, master in (SPI mode)
P2.1/UCA0SOMI/UCA0RXD/TB0.5/
DMAE0
USCI_A0: Receive data (UART mode)
32
BSL receive (UART BSL)
Timer_B TB0 CCR5 capture: CCI5B input, compare: Out5 output
DMA external trigger input
General-purpose digital I/O
USCI_A0: Slave in, master out (SPI mode)
P2.0/UCA0SIMO/UCA0TXD/TB0.6/
TB0CLK
USCI_A0: Transmit data (UART mode)
33
BSL transmit (UART BSL)
Timer_B TB0 CCR6 capture: CCI6B input, compare: Out6 output
DVSS2
DVCC2
Timer_B TB0 clock signal TB0CLK input
34 Digital ground supply
35 Digital power supply
General-purpose digital I/O
ESI test signal 4
P1.3/ESITEST4/TA1.2/A3/C3
36 Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
Analog input A3
Comparator input C3
8
Terminal Configuration and Functions
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