MSP430FR5989-EP Datasheet, PDF (39/154 Pages) Texas Instruments – Mixed-Signal Microcontroller

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MSP430FR5989-EP
SLASEC9 – APRIL 2017
Table 4-20 lists the characteristics of the eUSCI in SPI slave mode.
Table 4-20. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)⁽¹⁾
t_STE,LEAD
PARAMETER
STE lead time, STE active to clock
TEST CONDITIONS
V_CC
2.2 V
3.0 V
MIN MAX UNIT
45
ns
40
t_STE,LAG
STE lag time, Last clock to STE inactive
2.2 V
2
ns
3.0 V
3
t_STE,ACC
STE access time, STE active to SOMI data out
2.2 V
3.0 V
45
ns
40
t_STE,DIS
STE disable time, STE inactive to SOMI high
impedance
2.2 V
3.0 V
50
ns
45
t_SU,SI
SIMO input data setup time
2.2 V
4
ns
3.0 V
4
t_HD,SI
SIMO input data hold time
2.2 V
7
ns
3.0 V
7
t_VALID,SO
SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
C_L = 20 pF
2.2 V
3.0 V
35
ns
35
t_HD,SO
SOMI output data hold time⁽³⁾
C_L = 20 pF
2.2 V
0
ns
3.0 V
0
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 4-17 and Figure 4-18.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams inFigure 4-17
and Figure 4-18.
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Specifications
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