MSP430FR5989-EP Datasheet, PDF (59/154 Pages) Texas Instruments – Mixed-Signal Microcontroller

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MSP430FR5989-EP
SLASEC9 – APRIL 2017
5.3.1 Peripherals in Low-Power Modes
Peripherals can be in different states that impact the achievable power modes of the device. The states
depend on the operational modes of the peripherals. The states are:
• A peripheral is in a high-frequency state if it requires or uses a clock with a "high" frequency of more
than 50 kHz.
• A peripheral is in a low-frequency state if it requires or uses a clock with a "low" frequency of 50 kHz or
less.
• A peripheral is in an unclocked state if it does not require or use an internal clock.
If the CPU requests a power mode that does not support the current state of all active peripherals, the
device does not enter the requested power mode and instead enters a power mode that still supports the
current state of the peripherals, unless an external clock is used. If an external clock is used, the
application must ensure that the correct frequency range for the requested power mode is selected.
Table 5-2. Peripheral States
PERIPHERAL
IN HIGH-FREQUENCY STATE⁽¹⁾
WDT
DMA ⁽⁴⁾
Clocked by SMCLK
Not applicable
RTC_C
Not applicable
LCD_C
Not applicable
Timer_A TAx
Clocked by SMCLK or
clocked by external clock >50 kHz
Timer_B TBx
Clocked by SMCLK or
clocked by external clock >50 kHz
eUSCI_Ax in
UART mode
Clocked by SMCLK
eUSCI_Ax in SPI
master mode
Clocked by SMCLK
eUSCI_Ax in SPI
slave mode
eUSCI_Bx in I²C
master mode
eUSCI_Bx in I²C
slave mode
Clocked by external clock >50 kHz
Clocked by SMCLK or
clocked by external clock >50 kHz
Clocked by external clock >50 kHz
eUSCI_Bx in SPI
master mode
Clocked by SMCLK
eUSCI_Bx in SPI
slave mode
Clocked by external clock >50 kHz
ESI
Clocked by SMCLK
ADC12_B
Clocked by SMCLK or by MODOSC
REF_A
Not applicable
COMP_E
CRC ⁽⁵⁾
MPY ⁽⁵⁾
AES ⁽⁵⁾
Not applicable
Not applicable
Not applicable
Not applicable
IN LOW-FREQUENCY STATE⁽²⁾
Clocked by ACLK
Not applicable
Clocked by LFXT
Clocked by ACLK or VLOCLK
Clocked by ACLK or
clocked by external clock ≤50 kHz.
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by ACLK
Clocked by ACLK
Clocked by external clock ≤50 kHz
Clocked by ACLK or
clocked by external clock ≤50 kHz
Clocked by external clock ≤50 kHz
Clocked by ACLK
Clocked by external clock ≤50 kHz
Clocked by ACLK or ESIOSC
Clocked by ACLK
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
IN UNCLOCKED STATE⁽³⁾
Not applicable
Waiting for a trigger
Not applicable
Not applicable
Clocked by external clock ≤50 kHz.
Clocked by external clock ≤50 kHz
Waiting for first edge of START bit
Not applicable
Clocked by external clock ≤50 kHz
Not applicable
Waiting for START condition or
clocked by external clock ≤50 kHz
Not applicable
Clocked by external clock ≤50 kHz
Not applicable
Waiting for a trigger
Always
Always
Not applicable
Not applicable
Not applicable
(1) Peripherals are in a state that requires or uses a clock with a "high" frequency of more than 50 kHz.
(2) Peripherals are in a state that requires or uses a clock with a "low" frequency of 50 kHz or less.
(3) Peripherals are in a state that does not require or does not use an internal clock.
(4) The DMA always transfers data in active mode but can wait for a trigger in any low-power mode. A DMA trigger during a low-power
mode will cause a temporary transition into active mode for the time of the transfer.
(5) Operates only during active mode and will delay the transition into a low-power mode until its operation is completed.
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