MSP430FR5989-EP Datasheet, PDF (22/154 Pages) Texas Instruments – Mixed-Signal Microcontroller

MSP430FR5989-EP
SLASEC9 – APRIL 2017
www.ti.com
4.12 Thermal Resistance Characteristics
THERMAL METRIC⁽¹⁾
MSP430FR5989-EP
RGC (VQFN)
UNIT
R_θJA
R_θJC(top)
R_θJB
Ψ_JT
Ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance, still air⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top thermal characterization parameter
Junction-to-board thermal characterization parameter
Junction-to-case (bottom) thermal resistance⁽⁵⁾
64 Pins
29.2
13.9
8.1
8.0
0.2
1.0
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
4.13 Timing and Switching Characteristics
4.13.1 Power Supply Sequencing
TI recommends powering the AVCC, DVCC, and ESIDVCC pins from the same source. At a minimum,
during power up, power down, and device operation, the voltage difference between AVCC, DVCC, and
ESIDVCC must not exceed the limits specified in Absolute Maximum Ratings. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
At power up, the device does not start executing code before the supply voltage reached V_SVSH+ if the
supply rises monotonically to this level.
Table 4-1 lists the power ramp requirements.
Table 4-1. Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)
V_{VCC_BOR–}
V_{VCC_BOR+}
PARAMETER
Brownout power-down level⁽¹⁾⁽²⁾
Brownout power-up level⁽²⁾
TEST CONDITIONS
| dDV_CC/d_t | < 3 V/s⁽³⁾
| dDV_CC/d_t | > 300 V/s⁽³⁾
| dDV_CC/d_t | < 3 V/s⁽⁴⁾
MIN
MAX UNIT
0.7
1.66
V
0
0.79
1.68 V
(1) In case of a supply voltage brownout, the device supply voltages must ramp down to the specified brownout power-down level
(V_{VCC_BOR-}) before the voltage is ramped up again to ensure a reliable device start-up and performance according to the data sheet
including the correct operation of the on-chip SVS module.
(2) Fast supply voltage changes can trigger a BOR reset even within the recommended supply voltage range. To avoid unwanted BOR
resets, the supply voltage must change by less than 0.05 V per microsecond (±0.05 V/µs). Following the data sheet recommendation for
capacitor C_DVCC should limit the slopes accordingly.
(3) The brownout levels are measured with a slowly changing supply. With faster slopes, the MIN level required to reset the device properly
can decrease to 0 V. Use the graph in Figure 4-6 to estimate the V_{VCC_BOR-} level based on the down slope of the supply voltage. After
removing V_CC, the down slope can be estimated based on the current consumption and the capacitance on DVCC: dV/dt = I/C where
dV/dt = slope, I = current, C = capacitance.
(4) The brownout levels are measured with a slowly changing supply.
22
Specifications
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