MSP430FR5989-EP Datasheet, PDF (13/154 Pages) Texas Instruments – Mixed-Signal Microcontroller

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MSP430FR5989-EP
SLASEC9 – APRIL 2017
4 Specifications
4.1 Absolute Maximum Ratings⁽¹⁾
over operating junction temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at DVCC and AVCC pins to V_SS
Voltage difference between DVCC and AVCC pins⁽²⁾
–0.3
4.1
V
±0.3
V
Voltage applied to any pin⁽³⁾
–0.3
V_CC + 0.3 V
(4.1 max)
V
Diode current at any device pin
Storage temperature, T_stg(4)
±2
mA
–55
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and FRAM.
(3) All voltage values are with respect to V_SS, unless otherwise noted.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
4.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
V_(ESD) Electrostatic discharge _{Charged-device model (CDM), per JEDEC specification JESD22-C101(2)}
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
4.3 Recommended Operating Conditions
Typical data are based on V_CC = 3 V, T_J = 25°C unless otherwise noted.
V_CC
V_SS
T_J
C_DVCC
f_SYSTEM
Supply voltage range applied at all DVCC, AVCC, and ESIDVCC pins^{(1) (2) (3)}
Supply voltage applied at all DVSS, AVSS, and ESIDVSS pins
Operating junction temperature
Capacitor value at DVCC and ESIDVCC⁽⁵⁾
Processor frequency (maximum MCLK
frequency) ⁽⁶⁾
No FRAM wait states (NWAITSx = 0)
With FRAM wait states (NWAITSx = 1)⁽⁸⁾
MIN
1.8 ⁽⁴⁾
–55
1_–20%
0
0
NOM
0
MAX
3.6
95
8 ⁽⁷⁾
16 ⁽⁹⁾
UNIT
V
V
°C
µF
MHz
f_ACLK
f_SMCLK
Maximum ACLK frequency
Maximum SMCLK frequency
50 kHz
16⁽⁹⁾ MHz
(1) TI recommends powering the DVCC, AVCC, and ESIDVCC pins from the same source. At a minimum, during power up, power down,
and device operation, the voltage difference between DVCC, AVCC, and ESIDVCC must not exceed the limits specified in Absolute
Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
(2) See Table 4-1 for additional important information.
(3) Modules may have a different supply voltage range specification. See the specification of each module in this data sheet.
(4) The minimum supply voltage is defined by the supervisor SVS levels. See Table 4-2 for the exact values.
(5) Connect a low-ESR capacitor with at least the value specified and a maximum tolerance of 20% as close as possible to the DVCC and
ESIDVCC pins.
(6) Modules may have a different maximum input clock specification. See the specification of each module in this data sheet.
(7) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted.
(8) Wait states only occur on actual FRAM accesses; that is, on FRAM cache misses. RAM and peripheral accesses are always executed
without wait states.
(9) DCO settings and HF crystals with a typical value less than or equal to the specified MAX value are permitted. If a clock sources with a
larger typical value is used, the clock must be divided in the clock system.
Copyright © 2017, Texas Instruments Incorporated
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