LMH0318_15 Datasheet, PDF (8/57 Pages) Texas Instruments – LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

LMH0318
SNLS508 – SEPTEMBER 2015
www.ti.com
Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
3.3-V TOLERANT LVCMOS / LVTTL DC SPECIFICATIONS (SDA, SCL, LOS_INT_N)
V_IH25
V_IL
V_OL
I_IH
I_IL
SIGNAL DETECT
High level input voltage
Low level input voltage
Low level output voltage
Input high current
Input low current
2.5 V Supply Voltage
IOL = 1.25 mA
VIN = 2.5 V, VDD = 2.5 V
VIN = GND, VDD = 2.5 V
1.75
GND
20
-10
S_DH
Signal detect (default)
2.97 Gbps, EQ
Assert threshold level⁽¹⁾⁽²⁾ Pathological Pattern
2.97 Gbps, PLL
Pathological Pattern
2.97 Gbps, PRBS10
Pattern
S_DL
Signal detect (default)
2.97 Gbps EQ
De-assert threshold
Pathological Pattern
level ⁽¹⁾
2.97 Gbps, PLL
Pathological Pattern
2.97 Gbps, PRBS10
Pattern
HIGH SPEED RECEIVE RX INPUTS (IN_n+, IN_n-)
R_RD
DC Input differential
resistance
75
RL_RX-SDD
Input differential return
loss ^{(3) (4)}
Measured with the device
powered up.
SDD11 10 MHz to 2 GHz
SDD11 2 GHz to 3 GHz
RL_RX-SCD
Differential to common
mode Input
conversion ^{(3) (4)}
Measure with the device
powered up.SCD11, 10
MHz to 3 GHz
HIGH SPEED OUTPUTS (OUT_n+, OUT_n-)
V_{VOD_OUT1}
Output differential
voltage ^{(3) (4)}
Default setting, 8T clock
pattern
400
V_{VOD_OUT1_DE}
De-emphasis Level
VOD = 600mV, maximum
De-Emphasis with 16T
clock pattern
V_{VOD_OUT1_CLK}
Clock output differential
voltage
2.97 GHz,1.485 GHz, and
270 MHz
V_{VOD_OUT0}
Output single ended
Default setting
voltage at OUT0+ with
720
OUT0- terminated⁽⁵⁾⁽³⁾
R_{DIFF_OUT1}
DC output differential
resistance
TYP
22
22
22
16
16
9
100
-14
-6.5
-20
MAX
3.6
0.8
0.4
40
10
UNIT
V
V
V
μA
μA
mV_P-P
mV_P-P
mV_P-P
mV_P-P
mV_P-P
mV_P-P
125
Ω
dB
dB
dB
600
700
mV_P-P
-9
dB
560
mV_P-P
800
880
mV_P-P
100
Ω
(1) Data with extraordinarily long periods of high-frequency 1010 data, and for long, lossy channels, the signal amplitude at the input to the
device may be severely attenuated by the channel and may fall below the signal detect assert and/or de-assert thresholds.
(2) The voltage noise on the receiver inputs which has an amplitude larger than the signal detect assert threshold may trigger a signal
detect assert condition
(3) These limits are ensured by bench characterization and are not production tested.
(4) Dependent on board layout. Characterization data was measured with LMH1218EVM evaluation board
(5) ATE Production tested using DC method. Apply differential DC signal at the input and measure OUT0P amplitude. OUT0N terminated in
75 Ohm.
8
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