LMH0318_15 Datasheet, PDF (22/57 Pages) Texas Instruments – LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

LMH0318
SNLS508 – SEPTEMBER 2015
www.ti.com
8.3.7.7.3 SPI Read Transaction Format
An SPI read transaction is 34 bits per device consisting of two 17-bit frames. The first 17-bit read transaction,
first frame, shifts in the address to be read, followed by a dummy transaction, second frame, to shift out the 17-
bit read data. The R/W bit is 1 for the read transaction, as shown in Figure 11.
The first 17 bits from the read transaction specifies 1-bit of RW and 8-bits of address A7-A0. The eight 1’s
following the address are ignored. The second dummy transaction acts like a read operation on address 0xFF
and needs to be ignored. However, the transaction is necessary in order to shift out the read data D7-D0 in the
last 8 bits of the MISO output.
The signal timing for a SPI read transaction is shown in Figure 11. As with the SPI write, the “prime” values on
MISO during the first 16 clocks are a don’t-care for this portion of the transaction. Note, that the values shifted
out on MISO during the last 17 clocks reflect the read address and 8-bit read data for the current transaction.
SS_N
(host)
t_SSOF
SCK
(host)
MOSI
(host)
t_SSSU t_PH
t_PL
t_H
t_SU
1 A7 A6 A5 A4 A3 A2 A1 A0
MISO
(device)
'RQ¶W&DUH
³8X1´
t_SSH
³17X1´
tod
tozd
1
A
7
A
6
A
5
A
4
A
3
A
2
AA
10
D
7
D DD
6 54
D DD D
3 21 0
Figure 11. Signal Timing for a SPI Read Transaction
t_SSOF
todz
22
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