LMH0318_15 Datasheet, PDF (19/57 Pages) Texas Instruments – LMH0318 3 Gbps HD/SD SDI Reclocker with Integrated Cable Driver

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LMH0318
SNLS508 – SEPTEMBER 2015
8.3.7.6 SMBus READ/WRITE Transaction
The System Management Bus (SMBus) is a two-wire serial interface through which various system component
chips can communicate with the master. Slave devices are identified by having a unique device address. The
two-wire serial interface consists of SCL and SDA signals. SCL is a clock output from the Master to all of the
Slave devices on the bus. SDA is a bidirectional data signal between the Master and Slave devices. The
LMH0318 SMBUS SCL and SDA signals are open drain and require external pull up resistors.
Start and Stop:
The Master generates Start and Stop conditions at the beginning and end of each transaction.
• Start: High to low transition (falling edge) of SDA while SCL is high
• Stop: Low to high transition (rising edge) of SDA while SCL is high
Figure 3. Start and Stop Conditions
The Master generates 9 clock pulses for each byte transfer. The 9th clock pulse constitutes the ACK cycle. The
transmitter releases SDA to allow the receiver to send the ACK signal. An ACK is when the device pulls SDA
low, while a NACK is recorded if the line remains high.
Figure 4. Acknowledge (ACK)
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